/TRACY A WARREN/Primary Examiner, Art Unit 2137 Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to Applicant' s communication filed 12/23/2025 in response to the Office action dated 9/23/2025. Claims 1, 3-4, 8-9, and 15 have been amended. Claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 8-17 are rejected under 35 U.S.C 103 as being unpatentable over Agrawal et al. (US 20220405253 A1), hereinafter Agrawal, in view of Sakata et al. (US 20210073404 A1), hereinafter Sakata.
Regarding claim 1, Agrawal teaches a storage drive connectable to a host (Paragraphs 70, 77; Fig. 1, source storage 200 connected to source host system 100S including live migration server 100b),
the storage drive comprising: a drive memory; a storage medium; and a controller (Paragraphs 76, 79; Fig. 1, source storage 200 includes source memory 230 [storage medium] and is managed by source storage controller 210a and live migration controller 210b within live migration storage device 250b [drive memory]) configured to:
manage a logical address space (Paragraph 71; Fig. 1, source storage 200 includes logical block addresses LBAs);
receive, from the host, a read request that designates a first logical address range in the logical address space (Paragraphs 52, 77, 82, 84; Fig. 1, live migration server 100b [host] sends a live migration operation (including a live migration copy read operation) corresponding to LBAs within a namespace [address range] in source storage 200 to live migration controller 210b);
in accordance with the read request, read, from the storage medium to the drive memory, one or more pieces of valid data stored in one or more logical addresses, respectively, the one or more logical addresses being used by the host among a plurality of logical addresses included in the first logical address range (Paragraphs 82-84, 96; Figs. 1 and 2, copying valid data in LBAs of the namespace [address range] from source storage 200 to live migration controller 210b of live migration storage device 250b [drive memory] (via host data fetch 213) as part of a live migration copy read operation/process);
in accordance with the read request, transfer, from the drive memory to a host memory included in the host, first information indicating whether or not each of the plurality of logical addresses is used by the host (Paragraphs 82-84, 95-96; Figs. 1 and 2, creating first bitmap [first information] M1 which designates valid, relevant data [used by host] in LBAs and sending a copy of M1 from live migration controller 210b of live migration storage device 250b [drive memory] to live migration server 100b [host] (via host bitmap fetch 212) as part of a live migration copy read operation/process); and
in accordance with the read request, transfer either a plurality of pieces of data or the one or more pieces of valid data, the plurality of pieces of data respectively corresponding to the plurality of logical addresses and including the one or more pieces of valid data (Paragraphs 83-84; Fig. 1, as part of a live migration copy read operation, copying [transferring] relevant, valid data corresponding to LBAs as indicated by bitmap M1).
Agrawal does not explicitly teach to transfer, to the host memory, either a plurality of pieces of data or the one or more pieces of valid data, the host memory including a plurality of storage areas that respectively correspond to the plurality of logical addresses, the one or more pieces of valid data being transferred to one or more storage areas among the plurality of storage areas that respectively correspond to the one or more logical addresses.
However, Sakata teaches transfer, to the host memory, either a plurality of pieces of data or the one or more pieces of valid data (Paragraph 63; Fig. 1, temporarily storing user data (such as valid data) in host memory buffer HMB 221),
the host memory including a plurality of storage areas that respectively correspond to the plurality of logical addresses (Paragraphs 80-83; Fig. 4, HMB 221 includes buffer regions 61, 62, 63 [storage areas] which are accessed via corresponding virtual memory addresses HADDR0-HADDR2),
the one or more pieces of valid data being transferred to one or more storage areas among the plurality of storage areas that respectively correspond to the one or more logical addresses (Paragraphs 63, 80-83; Fig. 4, storing user data (such as valid data) within HMB 221’s buffer regions 61, 62, 63 which are accessed via corresponding virtual memory addresses HADDR0-HADDR2).
Agrawal and Sakata are analogous art because they are in the same field of endeavor, that being managing data movement in nonvolatile memory. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the storage drive of Agrawal to further include the transfer of pieces of data to the host memory according to the teachings of Sakata. The motivation for doing so would have been to improve the handling of large amounts of data without increasing the capacity/cost of the storage drive (Sakata, Paragraphs 62-63).
Regarding claim 2, Agrawal teaches the storage drive according to claim 1 including first information (Paragraphs 82-84; Fig. 1, bitmap M1),
the plurality of pieces of data, the one or more pieces of valid data (Paragraphs 83-84; Fig. 1, valid data in LBAs as indicated bitmap M1),
and the read request (Paragraph 84, live migration copy read operation).
Agrawal does not explicitly teach wherein a storage area of the host memory includes a first buffer capable of storing the first information and a second buffer capable of storing the plurality of pieces of data, the read request further designates a first buffer address indicative of the first buffer and a second buffer address indicative of the second buffer, and the controller is configured to: transfer the first information to the first buffer based on the first buffer address; and transfer either the plurality of pieces of data or the one or more pieces of valid data to the second buffer based on the second buffer address.
However, Sakata teaches wherein a storage area of the host memory includes a first buffer capable of storing the first information (Paragraphs 63, 80; Fig. 4, HMB 221 includes a first buffer region 61 which can store an address translation table (such as first information)) and
a second buffer capable of storing the plurality of pieces of data (Paragraphs 63, 80; Fig. 4, HMB 221 includes a second buffer region 62 which can store user data (such as valid data)),
the read request further designates a first buffer address indicative of the first buffer and a second buffer address indicative of the second buffer (Paragraphs 80, 90, 94; Figs. 1 and 4, reading and caching user data to HMB 221 based on HMB address translation table 151 including buffer addresses HADDR0 and HADDR1 [first and second buffer addresses, respectively]), and the controller is configured to:
transfer the first information to the first buffer based on the first buffer address (Paragraphs 63, 80; Fig. 4, an address translation table (such as first information) may be stored in HMB 221 within first buffer region 61 accessed via buffer address HADDR0); and
transfer either the plurality of pieces of data or the one or more pieces of valid data to the second buffer based on the second buffer address (Paragraphs 63, 80; Fig. 4, user data (such as valid data) may be stored in HMB 221 within second buffer region 62 accessed via buffer address HADDR1).
Agrawal and Sakata are analogous art because they are in the same field of endeavor, that being managing data movement in nonvolatile memory. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the storage drive of Agrawal to further include the first and second buffers according to the teachings of Sakata. The motivation for doing so would have been to improve the handling of large amounts of data without increasing the capacity/cost of the storage drive (Sakata, Paragraphs 62-63).
Regarding claim 3, Agrawal in view of Sakata teaches the storage drive according to claim 2, wherein the second buffer includes the plurality of storage areas that correspond to the plurality of logical addresses, respectively (Sakata, Paragraphs 81-83; Fig. 4, second buffer region 62 consists of three MPS regions 62-1, 62-2, 62-3 [storage areas] which correspond to logical host addresses HADDR1, HADDR1+4KB, HADDR1+8KB, respectively, in HMB address translation table 151), and
the controller is further configured to, in a case where the plurality of pieces of data are transferred to the second buffer, transfer the plurality of pieces of data to the plurality of storage areas, respectively (Sakata, Paragraphs 81, 94; Fig. 4, storing read user data to HMB 221 including second buffer region 62 consisting of MPS regions 62-1, 62-2, 62-3 [storage areas]).
Regarding claim 4, Agrawal in view of Sakata teaches the storage drive according to claim 2, wherein the second buffer includes the plurality of storage areas that corresponds to the plurality of logical addresses, respectively (Sakata, Paragraphs 81-83; Fig. 4, second buffer region 62 consists of three MPS regions 62-1, 62-2, 62-3 [storage areas] which correspond to logical host addresses HADDR1, HADDR1+4KB, HADDR1+8KB, respectively, in HMB address translation table 151),
a first piece of valid data among the one or more pieces of valid data is data stored in an i-th logical address among the plurality of logical addresses, i being an integer from one to a number of the plurality of logical addresses (Sakata, Paragraph 87; Fig. 4, data in second buffer region 62 is stored in logical addresses HADDR1 [1st logical address] to HADDR1+8KB [number of logical addresses]), and
the controller is further configured to, in a case where the one or more pieces of valid data are transferred to the second buffer, transfer the first piece of valid data to an i-th storage area among the plurality of storage areas (Sakata, Paragraphs 81, 94; Fig. 4, storing read user data to HMB 221 including second buffer region 62 starting at MPS region 62-1 [storage area]).
Regarding claim 8, Agrawal teaches a storage drive connectable to a host (Paragraphs 70, 77; Fig. 1, target storage 200 connected to source host system 100S including live migration server 100b),
the storage drive comprising: a storage medium; and a controller (Paragraphs 73, 79; Fig. 1, target storage 300 includes target memory 330 and is managed by target storage controller 210c and live migration controller 210b) configured to:
manage a logical address space (Paragraph 71; Fig. 1, target storage 300 includes logical block addresses LBAs);
receive, from the host, a write request that designates a first logical address range in the logical address space (Paragraphs 77, 82, 84; Fig. 1, live migration server 100b [host] sends a live migration operation (including a live migration copy write operation) corresponding to LBAs in target storage 300 to live migration controller 210b);
in accordance with the write request, transfer first information indicating whether each of a plurality of logical addresses included in the first logical address range is used by the host (Paragraphs 82-84, 96; Fig. 1, as part of a live migration copy write operation/process, transferring first bitmap [first information] M1 which designates valid, relevant data [used by host] in LBAs);
in accordance with the write request, transfer either a plurality of pieces of data that correspond to the plurality of logical addresses, respectively, or one or more pieces of valid data among the plurality of pieces of data (Paragraphs 82-84; Fig. 1, as part of a live migration copy write operation, copying [transferring] relevant, valid data); and
write at least the one or more pieces of valid data to the storage medium, based on the first information (Paragraphs 82-83; Fig. 1, copying [writing] valid data to target storage 300 based on first bitmap M1 [first information]).
Agrawal does not explicitly teach a drive memory; to transfer, from a host memory included in the host to the drive memory, first information; and to transfer, from the host memory to the drive memory, either a plurality of pieces of data or one or more pieces of valid data.
However, Sakata teaches a drive memory (Paragraph 40; Fig. 1, SSD 3);
to transfer, from a host memory included in the host to the drive memory, first information (Paragraphs 63, 108-109; Fig. 1, transferring data (such as first information) stored in HMB 221 to SSD 3), and
to transfer, from the host memory to the drive memory, either a plurality of pieces of data or one or more pieces of valid data (Paragraphs 63, 108-109; Fig. 1, transferring user data (such as valid data) stored in HMB 221 to SSD 3).
Agrawal and Sakata are analogous art because they are in the same field of endeavor, that being managing data movement in nonvolatile memory. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the storage drive of Agrawal to further include the drive memory and the transfer of pieces of data and first information from host memory to the drive memory according to the teachings of Sakata. The motivation for doing so would have been to improve the handling of large amounts of data without increasing the capacity/cost of the storage drive (Sakata, Paragraphs 62-63).
Regarding claim 9, Agrawal teaches the storage drive according to claim 8 including first information (Paragraphs 82-84; Fig. 1, bitmap M1),
the plurality of pieces of data, the one or more pieces of valid data (Paragraphs 83-84; Fig. 1, valid data in LBAs as indicated bitmap M1),
and the write request (Paragraph 84, live migration copy write operation).
Agrawal does not explicitly teach wherein a storage area of the host memory includes a first buffer capable of storing the first information and a second buffer capable of storing the plurality of pieces of data, the write request further designates a first buffer address indicative of the first buffer and a second buffer address indicative of the second buffer, and the controller is configured to: transfer the first information from the first buffer based on the first buffer address; and transfer either the plurality of pieces of data or the one or more pieces of valid data from the second buffer based on the second buffer address.
However, Sakata teaches wherein a storage area of the host memory includes a first buffer capable of storing the first information (Paragraphs 63, 80; Fig. 4, HMB 221 includes a first buffer region 61 which can store an address translation table (such as first information)) and
a second buffer capable of storing the plurality of pieces of data (Paragraphs 63, 80; Fig. 4, HMB 221 includes a second buffer region 62 which can store user data (such as valid data)),
the write request further designates a first buffer address indicative of the first buffer and a second buffer address indicative of the second buffer (Paragraphs 80, 108-109; Figs. 1 and 4, transmitting [writing] data from HMB 221 to SSD 3 via addresses in HMB translation table 151 including buffer addresses HADDR0 and HADDR1 [first and second buffer addresses, respectively]), and the controller is configured to:
transfer the first information from the first buffer based on the first buffer address (Paragraphs 63, 80, 108-109; Figs. 1 and 4, an address translation table (such as first information) stored in HMB 221 within first buffer region 61 at address HADDR0 may be transmitted from HMB 221 to SSD 3); and
transfer either the plurality of pieces of data or the one or more pieces of valid data from the second buffer based on the second buffer address (Paragraphs 63, 80, 108-109; Figs. 1 and 4, user data (such as valid data) stored in HMB 221 within second buffer region 62 at address HADDR1 may be transmitted from HMB 221 to SSD 3).
Agrawal and Sakata are analogous art because they are in the same field of endeavor, that being managing data movement in nonvolatile memory. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the storage drive of Agrawal to further include the first and second buffers according to the teachings of Sakata. The motivation for doing so would have been to improve the handling of large amounts of data without increasing the capacity/cost of the storage drive (Sakata, Paragraphs 62-63).
Regarding claim 10, Agrawal in view of Sakata teaches the storage drive according to claim 9, wherein the second buffer includes a plurality of storage areas that store the plurality of pieces of data, respectively (Sakata, Paragraphs 63, 81; Fig. 4, user data may be stored in second buffer region 62 consisting of three MPS regions 62-1, 62-2, 62-3 [storage areas]), and
the controller is further configured to, in a case where the plurality of pieces of data are transferred from the second buffer, transfer the plurality of pieces of data from the plurality of storage areas, respectively (Sakata, Paragraphs 81, 108-109; Figs. 1 and 4, transferring data from second buffer region 62 consisting of MPS regions 62-1, 62-2, 62-3 [storage areas] to SSD 3).
Regarding claim 11, Agrawal in view of Sakata teaches the storage drive according to claim 9, wherein the second buffer includes a plurality of storage areas that store the plurality of pieces of data, respectively (Sakata, Paragraphs 63, 81; Fig. 4, user data may be stored in second buffer region 62 consisting of three MPS regions 62-1, 62-2, 62-3 [storage areas]),
a first piece of valid data among the one or more pieces of valid data is data stored in an i-th logical address among the plurality of logical addresses, i being an integer from one to a number of the plurality of logical addresses (Sakata, Paragraph 87; Fig. 4, data in second buffer region 62 is stored in logical addresses HADDR1 [1st logical address] to HADDR1+8KB [number of logical addresses]), and
the controller is further configured to, in a case where the one or more pieces of valid data are transferred from the second buffer, transfer the first piece of valid data from an i-th storage area among the plurality of storage areas (Sakata, Paragraphs 81, 108-109; Figs. 1 and 4, transmitting data from second buffer region 62 starting at MPS region 62-1 [storage area] to SSD 3).
Regarding claim 12, Agrawal in view of Sakata teaches the storage drive according to claim 8, wherein the controller is configured to: receive, from the host, a read request that designates a second logical address range in the logical address space (Agrawal, Paragraphs 77, 82, 84; Fig. 1, live migration server 100b [host] sends a live migration operation [including a live migration copy read operation] corresponding to LBAs in source storage 200 to live migration controller 210b);
transfer, to the host memory, second information indicating whether or not each of a plurality of second logical addresses included in the second logical address range is used by the host (Agrawal, Paragraphs 82-84; Fig. 1, creating bitmap [second information] M1 which designates valid, relevant data [used by host] in LBAs and sending a copy of M1 to live migration server 100b [host]);
read, from the storage medium, one or more second pieces of valid data stored in one or more second logical addresses, respectively, the one or more second logical addresses being used by the host among the plurality of second logical addresses (Agrawal, Paragraphs 83-84; Fig. 1, copying valid data in LBAs from source storage 200 via a live migration copy read operation); and
transfer, to the host memory (Sakata, Paragraph 63; Fig. 1, temporarily storing user data in host memory buffer HMB 221),
either a plurality of second pieces of data or the one or more second pieces of valid data, the plurality of second pieces of data respectively corresponding to the plurality of second logical addresses and including the one or more second pieces of valid data (Agrawal, Paragraphs 83-84; Fig. 1, copying [transferring] relevant, valid data corresponding to LBAs).
Regarding claim 13, Agrawal in view of Sakata teaches the storage drive according to claim 12, wherein a storage area of the host memory includes a first buffer capable of storing the second information (Sakata, Paragraphs 63, 80; Fig. 4, HMB 221 includes a first buffer region 61 which can store an address translation table (such as second information)) and
a second buffer capable of storing the plurality of second pieces of data (Sakata, Paragraphs 63, 80; Fig. 4, HMB 221 includes a second buffer region 62 which can store user data (such as valid data)),
the read request further designates a first buffer address indicative of the first buffer and a second buffer address indicative of the second buffer (Sakata, Paragraphs 90, 94; Figs. 1 and 4, reading and caching user data to HMB 221 based on HMB address translation table 151 including buffer addresses HADDR0 and HADDR1 [first and second buffer addresses, respectively]), and the controller is further configured to:
transfer the second information to the first buffer based on the first buffer address (Sakata, Paragraphs 63, 80; Fig. 4, an address translation table (such as second information) may be stored in HMB 221 within first buffer region 61 accessed via buffer address HADDR0); and
transfer either the plurality of second pieces of data or the one or more second pieces of valid data to the second buffer based on the second buffer address (Sakata, Paragraphs 63, 80; Fig. 4, user data may be stored in HMB 221 within second buffer region 62 accessed via buffer address HADDR1).
Regarding claim 14, Agrawal in view of Sakata teaches the storage drive according to claim 13, wherein the second buffer includes a plurality of storage areas that correspond to the plurality of logical addresses, respectively (Sakata, Paragraphs 81-83; Fig. 4, second buffer region 62 consists of three MPS regions 62-1, 62-2, 62-3 [storage areas] which correspond to logical host addresses in HMB address translation table 151),
a first piece of valid data among the one or more pieces of valid data is data stored in an i-th logical address among the plurality of logical addresses, i being an integer from one to a number of the plurality of logical addresses (Sakata, Paragraph 87; Fig. 4, data in second buffer region 62 is stored in logical addresses HADDR1 [1st logical address] to HADDR1+8KB [number of logical addresses]), and
the controller is further configured to: in a case where the plurality of pieces of data are transferred to the second buffer, transfer the plurality of pieces of data to the plurality of storage areas, respectively (Sakata, Paragraphs 81, 94; Fig. 4, storing read user data to HMB 221 including second buffer region 62 consisting of MPS regions 62-1, 62-2, 62-3 [storage areas]); and
in a case where the one or more pieces of valid data are transferred to the second buffer, transfer the first piece of valid data to an i-th storage area among the plurality of storage areas (Sakata, Paragraphs 81, 94; Fig. 4, storing read user data to HMB 221 including second buffer region 62 starting at MPS region 62-1 [storage area]).
Regarding claim 15, Agrawal teaches a storage drive connectable to a host (Paragraphs 70, 77; Fig. 1, target storage 200 connected to source host system 100S including live migration server 100b),
the storage drive comprising: a storage medium; and a controller (Paragraphs 73, 79; Fig. 1, target storage 300 includes target memory 330 and is managed by target storage controller 210c and live migration controller 210b) configured to:
manage a logical address space (Paragraph 71; Fig. 1, target storage 300 includes logical block addresses LBAs);
receive a write request from the host (Paragraphs 77, 82, 84; Fig. 1, live migration server 100b [host] sends a live migration operation (including a live migration copy write operation) to live migration controller 210b);
in accordance with the write request, transfer first information indicating whether each of a plurality of logical addresses included in a first logical address range in the logical address space stores valid data (Paragraphs 82-84, 96; Fig. 1, as part of a live migration copy operation/process, transferring first bitmap [first information] M1 which designates valid, relevant data [used by host] in LBAs),
in accordance with the write request, transfer second information that includes a first address indicative of a start of the first logical address range, a second address indicative of an end of the first logical address range, and a first number of pieces of valid data stored in the first logical address range (Paragraphs 82-84, 96; Fig. 1, as part of a live migration copy operation/process, transferring first bitmap M1 which includes the entire LBA namespace of a drive [first logical address range including a start and end LBA] as well as a number of LBAs storing valid data within the drive);
in accordance with the write request, transfer the first number of pieces of valid data (Paragraphs 82-84; Fig. 1, as part of a live migration copy operation, copying [transferring] relevant, valid data); and
write the first number of pieces of valid data to the storage medium, based on the first information (Paragraphs 82-83; Fig. 1, copying [writing] valid data to target storage 300 based on first bitmap M1 [first information]).
Agrawal does not explicitly teach to a drive memory; transfer, from a host memory included in the host to the drive memory, first information; transfer, from the host memory to the drive memory, second information; and transfer the first number of pieces of valid data from the host memory to the drive memory.
However, Sakata teaches a drive memory (Paragraph 40; Fig. 1, SSD 3);
transfer, from a host memory included in the host to the drive memory, first information (Paragraphs 63, 108-109; Fig. 1, transferring data (such as first information) stored in HMB 221 to SSD 3);
transfer, from the host memory to the drive memory, second information (Paragraphs 63, 108-109; Fig. 1, transferring data (such as second information) stored in HMB 221 to SSD 3); and
transfer the first number of pieces of valid data from the host memory to the drive memory (Paragraphs 63, 108-109; Fig. 1, transferring user data (such as valid data) stored in HMB 221 to SSD 3).
Agrawal and Sakata are analogous art because they are in the same field of endeavor, that being managing data movement in nonvolatile memory. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the storage drive of Agrawal to further include the drive memory and the transfer of pieces of data, first information, and second information from host memory to the drive memory according to the teachings of Sakata. The motivation for doing so would have been to improve the handling of large amounts of data without increasing the capacity/cost of the storage drive (Sakata, Paragraphs 62-63).
Regarding claim 16, Agrawal teaches the storage drive according to claim 15 including first information (Paragraphs 82-84; Fig. 1, bitmap M1 designates valid LBAs),
second information (Paragraphs 82-83; Fig. 1, bitmap M1 includes the start and end LBAs of a storage drive as well as a number of valid LBAs)
the one or more pieces of valid data (Paragraphs 83-84; Fig. 1, valid data in LBAs as indicated bitmap M1),
and the write request (Paragraph 84, live migration copy write operation).
Agrawal does not explicitly teach wherein a storage area of the host memory includes a first buffer storing the first information, a second buffer storing the first number of pieces of valid data, and a third buffer storing the second information, the write request further designates a first buffer address indicative of the first buffer, a second buffer address indicative of the second buffer, and a third buffer address indicative of the third buffer, and the controller configured to: transfer the first information from the first buffer based on the first buffer address; transfer the first number of pieces of valid data from the second buffer based on the second buffer address; and transfer the second information from the third buffer based on the third buffer address.
However, Sakata teaches wherein a storage area of the host memory includes a first buffer storing the first information (Paragraphs 63, 80; Fig. 4, HMB 221 includes a first buffer region 61 which can store an address translation table (such as first information)),
a second buffer storing the first number of pieces of valid data (Paragraphs 63, 80; Fig. 4, HMB 221 includes a second buffer region 62 which can store user data (such as valid data)), and
a third buffer storing the second information (Paragraphs 63, 80; Fig. 4, HMB 221 includes a second buffer region 62 which can store a counter of valid data in each block (such as second information)),
the write request further designates a first buffer address indicative of the first buffer, a second buffer address indicative of the second buffer, and a third buffer address indicative of the third buffer (Paragraphs 80, 108-109; Figs. 1 and 4, transmitting [writing] data from HMB 221 to SSD 3 via addresses in HMB translation table 151 including buffer addresses HADDR0, HADDR1, and HADDR2 [first, second, and third buffer addresses, respectively]), and the controller configured to:
transfer the first information from the first buffer based on the first buffer address (Paragraphs 63, 80, 108-109; Figs. 1 and 4, an address translation table (such as first information) stored in HMB 221 within first buffer region 61 at address HADDR0 may be transmitted from HMB 221 to SSD 3);
transfer the first number of pieces of valid data from the second buffer based on the second buffer address (Paragraphs 63, 80, 108-109; Figs. 1 and 4, user data (such as valid data) stored in HMB 221 within second buffer region 62 at address HADDR1 may be transmitted from HMB 221 to SSD 3); and
transfer the second information from the third buffer based on the third buffer address (Paragraphs 63, 80, 108-109; Figs. 1 and 4, counter for valid data in blocks [such as second information] stored in HMB 221 within third buffer region 63 at address HADDR2 may be transmitted from HMB 221 to SSD 3).
Agrawal and Sakata are analogous art because they are in the same field of endeavor, that being managing data movement in nonvolatile memory. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the storage drive of Agrawal to further include the first, second, and third buffers according to the teachings of Sakata. The motivation for doing so would have been to improve the handling of large amounts of data without increasing the capacity/cost of the storage drive (Sakata, Paragraphs 62-63).
Regarding claim 17, Agrawal in view of Sakata teaches the storage drive according to claim 16, wherein the second buffer includes the first number of storage areas storing the first number of pieces of valid data, respectively (Sakata, Paragraphs 63, 81; Fig. 4, user data may be stored in second buffer region 62 consisting of three MPS regions 62-1, 62-2, 62-3 [storage areas]),
i-th piece of valid data among the first number of pieces of valid data is data stored in an i-th logical address used by the host from a head of the plurality of logical addresses, i being an integer from one to the first number (Sakata, Paragraph 87; Fig. 4, data in second buffer region 62 of HMB 221 [host] is stored in logical addresses starting at HADDR1 [head logical address] to HADDR1+8KB [number of logical addresses]), and
the controller is configured to transfer the first number of pieces of valid data from the first number of storage areas, respectively (Sakata, Paragraphs 81, 108-109; Figs. 1 and 4, transmitting data from second buffer region 62 consisting of MPS regions 62-1, 62-2, 62-3 [storage areas] to SSD 3).
Allowable Subject Matter
Claims 5-7 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 5 and 18 recite the limitations of (or similar thereof):
“wherein the read request further designates information by which a maximum number of pieces of valid data to be read from the first logical address range is identifiable, the controller is configured to, in a case where the first logical address range stores a first number of pieces of valid data, the first number being equal to or smaller than the maximum number: transfer, to the host memory, second information that includes a first address indicative of a start of the first logical address range, a second address indicative of an end of the first logical address range, and the first number; transfer the first information to the host memory; read the first number of pieces of valid data from the storage medium; and transfer the read first number of pieces of valid data to the host memory, and the controller is further configured to, in a case where the first logical address range stores a second number of pieces of valid data, the second number exceeding the maximum number: transfer information that includes the first address, a third address that is one-logical address before a first logical address at which a number obtained by counting pieces of valid data stored in the first logical address range in order from a head exceeds the maximum number, and the maximum number, to the host memory as the second information; transfer information indicating at least whether each of one or more logical addresses from the first address to the third address stores valid data, to the host memory as the first information; read, from the storage medium, the maximum number of pieces of valid data in order from a head of the plurality of pieces of data that are stored in the plurality of logical addresses, respectively; and transfer the read maximum number of pieces of valid data to the host memory.”
Claims 5 and 18 are deemed to be directed towards a nonobvious improvement over the invention published in Agrawal (US 20220405253 A1). Although Agrawal also teaches the transfer/migration of valid data, the prior art of record does not explicitly teach or render obvious the limitations above. Specifically, claims 5 and 18 set a maximum limit on the amount of valid data transferred, accommodating the host buffer capacity and improving memory management.
Claims 6-7 and 19-20 are dependent upon claims 5 and 18, respectively, and thus would be allowable for the same reasons as their respective parent claims.
Response to Arguments
Applicant’s arguments (see pages 17-21 of the remarks) filed 12/23/2025, with respect to the rejections of claims 1-4 and 8-17 under 35 U.S.C 103 have been fully considered, but are not persuasive.
The Applicant argues that Agrawal in view of Sakata does not teach the amended claim features. Firstly, the Applicant states that Agrawal does not disclose the trigger for transferring first data structure M1 (with respect to the amended limitations “in accordance with a/the read request”) nor does it disclose any further address range corresponding to first data structure M1 (with respect to the limitations “a read request that designates a first logical address range in the logical address space” and “a plurality of logical addresses included in the first logical address range”).
However, Agrawal teaches that the live migration process is a trigger for transferring the first data structure M1 (Paragraph 96; Fig. 1, during a stage of the live migration process, sending a copy of first data structure M1 from live migration controller 210b to live migration server 100b). In addition, Agrawal teaches an address range corresponding to the first data structure M1 (Paragraphs 52, 82; Fig. 1, first data structure M1 is a bit-map BMP which targets an entire storage namespace which includes logical block addresses LBAs).
Secondly, the Applicant states that Agrawal fails to discloses the limitation “in accordance with the read request, transfer, to the host memory, either a plurality of pieces of data or the one or more pieces of valid data, the plurality of pieces of data respectively corresponding to the plurality of logical addresses and including the one or more pieces of valid data, the host memory including a plurality of storage areas that respectively correspond to the plurality of logical addresses, the one or more pieces of valid data being transferred to one or more storage areas among the plurality of storage areas that respectively correspond to the one or more logical addresses”. Specifically, the Applicant argues that Agrawal uses the live migration server 100b (host) to copy the relevant data in response to the read request rather than the live migration controller 200b (storage device).
The rejection has been revised to clarify that Agrawal teaches the process of transferring valid data in accordance with a read request (Paragraphs 82-84; Fig. 1, copying [transferring] relevant, valid data in accordance with first data structure M1 in response to a live migration copy read operation) while Sakata teaches transferring the data to the host memory (Paragraph 63; Fig. 1, storing various data into host memory buffer 221).
Lastly, the Applicant argues that Sakata does not disclose any feature of storing “the first information” in the HMB 221.
However, although Sakata does not specifically disclose storing a bit-map such as the data structure M1 of Agrawal (which was used to teach “the first information”), Sakata does teach storing similar information (Sakata, Paragraph 63; Fig. 1, HMB 221 stores data for executing various processes). Since “the first information” was taught to be used in a live migration process by Agrawal (Agrawal, Paragraph 82, using first data structure M1 [first information] in a live migration process), the Examiner argues that “the first information” would fall under the category of “data for executing various processes” of Sakata.
Accordingly, the Examiner argues that the newly cited areas of the Agrawal and Sakata references teach the contested limitations and further notes any other arguments with respect to claims 1, 8, and 15 are consummate in scope with the argument above. Thus, the Examiner maintains the rejections set forth above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.M.P./Examiner, Art Unit 2137
/TRACY A WARREN/Primary Examiner, Art Unit 2137