Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .1
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18, 31-33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyake (US 20150061533 A1) in view of Voutsas (US 20040087066 A1).
Regarding claim 18:
Miyake (US 20150061533 A1) discloses a light-emitting device (Fig. 8) comprising: a substrate (display substrate); and a plurality of pixels on the substrate ([0119-0123]), the plurality of pixels being arranged in an array, wherein each of the plurality of pixels comprises (1) a light-emitting element (14), [ (2) a drive transistor (15), (3) a capacitor element (18) directly connected to a gate electrode of the drive transistor (([0119-0123]),), and (4) another capacitor element (53) directly connected to the capacitor element, wherein one of main terminals of the drive transistor is connected (electrically connected) to the light-emitting element (14) ([0119-0123]).
Note that Miyake does not specifically disclose wherein diffusion regions of the drive transistor are of a first conductivity type, wherein a gate electrode of the drive transistor is of a second conductivity type opposite to the first conductivity type, and wherein the gate electrode of the drive transistor comprises doped semiconductor.
Voutsas (US 20040087066 A1) discloses the diffusion regions (diffusion region of Source or drain of NPN transistor 306, Fig. 6) are of a first conductivity type (i.e. n-type), wherein the gate electrode is of the drive transistor comprises doped semiconductor (e.g. p -type) opposite to the first conductivity type ([0035], [0046] and Fig. 6).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyake with the teaching of Voutsas , thereby providing a high image quality by using with reduce off current of a transistor in the display device.
Regarding claim 31:
Miyake discloses a control unit (control unit corresponding to voltage driver) configured to control driving of the light-emitting device (([0119-0123]),).
Regarding claim 32:
Miyake in view of Voutsas discloses further comprising a switch transistor ((Fig. 8), wherein one of main terminals of the switch transistor is connected to another of the main terminals of the drive transistor see Miyake ([0119-0123]), wherein diffusion regions of the switch transistor are of the first conductivity type, and wherein a gate electrode of the switch transistor is of the first conductivity type (see Voustas0035], [0046] and Fig. 6). Same motivation as applied to claim 18.
Regarding claim 33:
Miyake in view of Voutsas discloses a capacitor element (606) connected to the gate electrode of the drive transistor (see Voustas0035], [0046] and Fig. 6). Same motivation as applied to claim 18.
2. Claim 19-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyake in view of Voutsas (US 20040087066 A1) further in view of park (US 20060221662 A1).
Regarding claim 19:
Miyake in view of Voutsas discloses wherein the drive transistor (6402) comprises a channel region (channel region of gate electrode) disposed between the diffusion regions of the drive transistor (i.e diffusion regions in source and drain region), wherein the switch transistor (6401) comprises a channel region (channel region with gate electrode of 6401) disposed between the diffusion regions of the switch transistor (i.e. diffusion region of 6401) (see Miyake ([0119-0123]), Fig. 8), and Voutsas, ([0035], [0046] and Fig. 6). Same motivation as applied to claim 18.
Miyake in view of Voustas does not specifically disclose wherein an impurity concentration of the channel region of the drive transistor is lower than an impurity concentration of the channel region of the switch transistor.
Park (US 20060221662 A1) discloses wherein an impurity concentration of a channel (n channel) region of the first transistor (Qd) is lower than an impurity concentration of a channel (p channel) region of the second transistor (Qs1) ([0052] The switching transistor Qs1 P-channel transistor, and driving transistor Qd are n-channel transistor, impurity concentrations of n channel are lower in n-channel transistor).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyake with the teaching of Voutsas and Park, thereby providing a high efficient data transmission in the display device.
Regarding claim 20:
Miyake in view of Voutsas and Park discloses wherein a channel region of the third transistor (Qs3) is of the first conductivity type (Park, [0052]), thereby providing and accurate data transmission in the display device.
Regarding claim 21:
Miyake in view of Voutsus discloses the first transistor (306, Fig. 6) and the second transistor (600) are arranged in a well (see Fig. 8a) (see Voutus, [0035], [0046] and Fig. 6), and
park (US 20060221662 A1) discloses an impurity concentration of a channel region of the first transistor is lower than an impurity concentration of the well (gate channel is n type) (park, [0052]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyake with the teaching of Voutsas and Park, thereby providing an accurate data transmission in the display device.
Regarding claim 22:
Miyake in view of Voutsas and park discloses wherein each of the plurality of pixels further comprises a select transistor (Qs5) configured to translate a signal voltage (Vgi, see Park Fig. 2), and wherein the gate electrode of the drive transistor (Td) is connected to the capacitor element (C2) (see Park, Fig. 2, [0051-0053]). Same motivation as recited in claim 19.
Regarding claim 23:
Miyake in view of Voutsas and Park discloses wherein diffusion regions (source and drain) of the select transistor (Qs5, Fig. 14) are of the first conductivity type (ntype), and a gate electrode of the third transistor is of the second conductivity type (ptype) (see, Park Fig. 2 [0052]. Same motivation as recited in claim 19.
Regarding claim 24:
Miyake in view of Voutsas and Park discloses wherein the select transistor (QS5) comprises a channel region disposed between the diffusion regions of the select transistor ([0100], Fig. 2), and wherein an impurity concentration of the channel region of the switch transistor is lower than an impurity concentration of the channel region of the select transistor (Park, Fig. 2, [0052 - 0055]). Same motivation as applied to claim 19.
Regarding claim 25:
Miyake in view of Voutsas and Park discloses wherein a channel region of the switch transistor (see switching transistors Qs1-Qs5 of the pixel shown in FIG. 14)) is of the first conductivity type (ptype) (Park, Fig. 2, [0052 - 0055]). Same motivation as applied to claim 19.
Regarding claim 26:
Miyake in view of Voutsas and Park discloses wherein one of main terminals of the select transistor (Qs5) is connected (connected through N2) to the gate electrode of the drive transistor (Qd) (Park, Fig. 2, [0052 - 0055]). Same motivation as applied to claim 19.
Regarding claim 27:
Miyake in view of Voutsas and Park discloses wherein an impurity concentration of a gate electrode of drive transistor (Qd) is lower than an impurity concentration of a channel region of the second transistor (Qs1) Park, Fig. 2, [0052 - 0055]). Same motivation as applied to claim 19.
Regarding claim 28:
Miyake in view of Voutsas and Park discloses wherein the drive transistor (Qd) is arranged between the light-emitting element and the switch transistor (Qs3). Park, Fig. 2, [0052 - 0055]). Same motivation as applied to claim 19.
Regarding claim 29:
Miyake in view of Voutsas and Park discloses wherein the substrate (110) comprises a semiconductor (Park, Fig.3, [0054 - 0055]). Same motivation as applied to claim 19.
Regarding claim 30:
Miyake in view of Voutsas and Park discloses wherein the drive transistor (Qd, Fig. 2, Park) comprises a channel region disposed between the diffusion regions of the drive transistor, wherein the switch transistor (Qs2) comprises a channel region disposed between the diffusion regions of the switch transistor wherein an insulation layer is arranged between the channel region and the gate electrode (see Fig.2, Park[) of the drive transistor and between the channel region of the switch transistor and the gate electrode of the switch transistor [(Park, Fig.3, [0054 - 0055]) and wherein the insulation layer comprises an oxide of the semiconductor ([0060] A gate insulating layer 140 made of silicon oxide (SiO.sub.x)) , (Park, Fig.3, [0054 - 0055]). Same motivation as applied to claim 19.
Responds to Applicant’s Argument
3. More specifically the Applicant argues that “Yamazaki in view of Voutsas does not specifically disclose the claim limitations as recited in claim 18.
However, Miyake (US 20150061533 A1) has been considered for further prosecution.
Miyake (US 20150061533 A1) in view of Voutsas (US 20040087066 A1) meet the limitations as recited in the claim 18.
Conclusion
15. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Inquiry
5. Any inquiry concerning this communication or earlier communication from the examiner should be directed to Shaheda Abdin whose telephone number is (571) 270-1673.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LunYi Lao could be reached at (571) 272-7671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAHEDA A ABDIN/Primary Examiner, Art Unit 2627
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