DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Masuda et al. (US 2007/0236293).
In regard to Claim 1:
Masuda discloses, in Figure 6, a bias circuit comprising:
a first bias transistor (41) that has a base (41 base) or a gate that is supplied with a first bias (22 connected to 41 base via 52 and 53), and an emitter (41 emitter) or a source that is configured to supply a bias to a first amplifier (31) through a first resistor circuit element (51);
a first diode (43) that has an anode (43 collector) that is connected to the base (41 base) or the gate of the first bias transistor (41), and a cathode (43 emitter) that is electrically connected to the emitter or the source of the first bias transistor (43 emitter is connected to 41 emitter via 54, 42 and 41);
a second resistor circuit element (53) that has a first end that is connected to the anode of the first diode (43 collector), and a second end that is connected to the cathode of the first diode (53 is connected to 43 emitter via 62); and
a capacitor (61) that has a first end that is connected to the anode of the first diode (43 collector), and a second end that is connected to ground (61 connected to ground),
wherein the cathode of the first diode (43 emitter) is electrically connected to ground (ground).
In regard to Claim 7:
Masuda discloses, in Figure 6, the bias circuit according to Claim 1, further comprising:
a third bias transistor (44) that has a base (44 base) or a gate that is supplied with a second bias (22 coupled through 56, 57 connected to 44 base), and an emitter (44 emitter) or a source that is configured to supply a bias to a third amplifier (32) through a seventh resistor circuit element (55), the third amplifier (32) being cascade-connected to the first amplifier (31);
a fourth diode (46) that has an anode that is connected to the base or the gate of the third bias transistor (46 collector connected to 44 base), and a cathode that is electrically connected to the emitter or the source of the third bias transistor (46 emitter connected to 44 emitter via 58, 45, and 44);
an eighth resistor circuit element (57) that has a first end that is connected to the anode of the fourth diode (57 connected to 46 collector), and a second end that is connected to the cathode of the fourth diode (57 connected to 46 emitter via 66); and
a capacitor (65) that has a first end that is connected to the anode of the fourth diode (65 connected to 46 collector), and a second end that is connected to ground (65 connected to ground),
wherein the cathode of the fourth diode is electrically connected to ground (46 emitter connected to ground).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuda et al. (US 2007/0236293), in view of Satou (US 2019/0190457).
In regard to Claim 2:
Masuda does not disclose the bias circuit according to Claim 1, further comprising: a second diode that has an anode, and a cathode that is connected to ground, wherein the cathode of the first diode is connected to the anode of the second diode.
Satou discloses, in Figure 1, further comprising: a second diode (D22) that has an anode (D22 collector), and a cathode that is connected to ground (D22 emitter connected to ground), wherein the cathode of the first diode (D21 emitter) is connected to the anode of the second diode (D22 collector).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the diodes taught by Satou in place of the diode taught by Masuda, in order to provide a larger change in gain (gain dispersion) relative to a change in a power supply voltage to be supplied to a transistor enables the use of a higher efficiency power supply voltage value while keeping gain flatness, since the greater the gain dispersion of a power amplifier circuit, the more preferable for improving the efficiency of the power amplifier circuit (Satou ¶ 0003).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuda et al. (US 2007/0236293), in view of Tsutsui et al. (US 2014/0285268).
In regard to Claim 3:
Masuda further discloses, in Figure 6, the bias circuit according to Claim 1, further comprising: a transistor (42) that has a collector (42 collector) or a drain, a base (42 base) or a gate, and an emitter or a source that is connected to ground (42 emitter connected to ground via 54); and wherein the cathode of the first diode (43 emitter) is connected to the collector or the drain of the transistor (43 emitter connected to 42 collector via ground and 63).
Masuda does not disclose a third resistor circuit element that is connected between the emitter or the source of the first bias transistor and the base or the gate of the transistor.
Tsutsui discloses, in Figure 4A, a third resistor circuit element (405) that is connected between the emitter or the source of the first bias transistor (405 connected to 402 emitter via 407) and the base or the gate of the transistor (401 base).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the resistor taught by Tsutsui with the bias transistors taught by Masuda, in order to compensate for insufficient bias which allows for the linearity of the RF amplifying circuit to be improved (Tsutsui ¶ 0103).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuda et al. (US 2007/0236293), in view of Honda et al. (US 2020/0052658).
In regard to Claim 4:
Masuda does not disclose the bias circuit according to Claim 1, further comprising: a third diode that has an anode that is connected to the emitter or the source of the first bias transistor, and a cathode that is connected to ground.
Honda et al. (US 2020/0052658) discloses, in Figure 7, further comprising: a third diode (Q6) that has an anode that is connected to the emitter or the source of the first bias transistor (Q6 collector connected to Q2a emitter), and a cathode that is connected to ground (Q6 emitter connected to ground via Q5a).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the diode taught by Honda with the bias circuit taught by Masuda, in order to provide a power amplifier circuit that matches impedances of an amplifier and the preceding circuit, with improved linearity of power gain (Honda ¶ 0007).
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuda et al. (US 2007/0236293), in view of Kuriyama (US 2005/0062541).
In regard to Claim 5:
Masuda does not disclose the bias circuit according to Claim 1, wherein the cathode of the first diode is connected to the emitter or the source of the first bias transistor, and wherein a fourth resistor circuit element is connected between the cathode of the first diode and the emitter or the source of the first bias transistor.
Kuriyama discloses, in Figure 4, wherein the cathode of the first diode (Q1 emitter) is connected to the emitter or the source of the first bias transistor (Q4 emitter via R5), and wherein a fourth resistor circuit element (R5) is connected between the cathode of the first diode (Q1 emitter) and the emitter or the source of the first bias transistor (Q4 emitter).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the resistor taught by Kuriyama with the diode and bias transistor taught by Masuda, in order to block the high-frequency signal from leaking to the bias circuit, therefore removing the influence of the high-frequency signal to the bias circuit (Kuriyama ¶ 0052).
In regard to Claim 6:
Masuda further discloses, in Figure 30, the bias circuit according to Claim 5, further comprising:
a second bias transistor (44) that has a base or a gate that is connected to the base or the gate of the first bias transistor (44 base is connected to 41 base), and an emitter or a source (44 emitter) that is configured to supply a bias to a second amplifier (32) through a fifth resistor circuit element (55),
wherein the first amplifier (31) and the second amplifier (32) form a differential pair (¶ 0169), wherein the cathode of the first diode (43 emitter) is connected to the emitter or the source of the second bias transistor (43 emitter connected to 44 emitter via 54, 42, and 44), and
wherein a sixth resistor circuit element (54) is connected between the cathode of the first diode (43 emitter) and the emitter or the source of the second bias transistor (43 emitter connected to 44 emitter via 54, 42, and 44).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ishimaru et al. (US 2008/0186099) discloses a bias circuit 22 in a power amplifier 1 is provided with a VBE-controlled voltage source circuit 20 and a Nagata current mirror circuit 21. The Nagata current mirror circuit 21 includes a transistor Tr5 and a transistor Tr6. The transistor Tr5 has its emitter grounded, its base connected to a control input terminal 17 via a resistor R3, and its collector connected to that base via a resistor R4. The transistor Tr6 has its emitter grounded, its base connected to the collector of the transistor Tr5, and its collector connected to the base of the transistor Tr3.
Hur et al. (US 2019/0158041) discloses the amplification circuit generally includes a first transistor, an input path coupled between an input node of the amplification circuit and a control input of the first transistor, and a feedforward path coupled between the input node and a feedforward node. In certain aspects, the amplification circuit may also include a first resistive device coupled between the feedforward node and the control input of the first transistor, a biasing circuit coupled to the feedforward node, and a low-impedance path coupled to the feedforward node.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOHN W POOS/Primary Examiner, Art Unit 2843
Prosecution Insights