Detailed Action
The instant application having Application No. 18/828,391 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner. This Office action is in response to the claims filed 4/13/26. Claims 1-20 are pending.
NOTICE OF PRE-AIA OR AIA STATUS
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
REJECTIONS NOT BASED ON PRIOR ART
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: write post-processing module, cache processing module, a read processing module and metadata processing module in claim 1-10. A review of applicant’s specification describes modules as software or hardware components, such as an FPGA or ASIC (para. 34).
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 11 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong (U.S. Patent Application Publication No. 2023/0073200), herein referred to as Jeong, in view of Pahwa et al. (U.S. Patent Application Publication No. 2020/0393975), herein referred to as Pahwa et al.
Referring to claim 1, Jeong discloses as claimed, a storage controller for managing a non-volatile memory device, the storage controller comprising: (see fig. 1, showing a memory system with a controller. See para. 20-21, where circuits and logic may comprise software or hardware. See fig. 3 and para. 133-137, where the controller includes various modules such as a flash translation layer and map manager): one or more processors configured to execute one or more instructions (see para. 21, where the circuitry or logic may comprise a processor), wherein the one or more instructions when executed by the one or more processors, individually or collectively, cause a write post-processing module configured to output a cache update request in response to a write completion (see para. 136-137, where a map update request may be sent after a write request); a cache processing module configured to output a cache update response based on the cache update request and release at least one of cache memory or buffer memory (see para. 151 and 174, where when a write command is completed, the memory device may issue a response to notify of a completion and the controller may release buffer memory. Also see para. 141, where when a map cache miss occurs during an update, the map manager may load a relevant map table. When there are a threshold number of dirty cache blocks, the dirty map table may be stored in the memory device. Also see para. 139, where garbage collection is performed to free blocks); and a metadata processing module configured to update mapping data, the mapping data indicating a correspondence between physical addresses and logical addresses (see para. 140-142, where the map manager may update map data such as a logical to physical address map table), wherein the one or more instructions when executed by the one or more processors, individually or collectively, further cause the write post-processing to based on the cache update response release the at least one of the cache memory and the buffer memory (see para. 151 and 174, where when a write command is completed, the memory device may issue a response to notify of a completion and the controller may release buffer memory.), determine whether the mapping data is updatable, and output a mapping update request based on the determination, and wherein the one or more instructions when executed by the one or more processors, individually or collectively, further cause the metadata processing module is further configured to update the mapping data in response to the mapping update request (see para. 140-142, where the map manager in the controller may not perform the update if the copying of a valid page is not completed normally. The map update operation is only performed if the latest map table still points to an old physical address).
Jeong disclose the claimed invention except for subsequent to the releasing the at least one of the cache memory and the buffer memory, determine whether the mapping data is updatable and output a mapping update request based on the determination.
Howver, Pahwa et al. disclose subsequent to the releasing the at least one of the cache memory and the buffer memory, determine whether the mapping data is updatable and output a mapping update request based on the determination (see para. 132-133 and fig. 13, where when a write hit is determined, the controller may discard the data by releasing a storage space in the buffer memory. Then after releasing the storage space in the buffer, the controller may update mapping information. Pahwa et al. is being combined with Jeong, which teaches the mapping of memory addresses involves the steps of determining whether the mapping data is updateable and outputting a mapping update request and mapping the addresses. Therefore, when combined, the combination would teach releasing data in the buffer and then subsequently determining whether the mapping data is updateable and outputting a mapping update request and mapping the addresses).
Jeong and Pahwa et al. are analogous art because they are from the same field of endeavor of memory systems (see Jeong, abstract, and Pahwa et al., abstract, regarding memory systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong to comprise subsequent to the releasing the at least one of the cache memory and the buffer memory, determine whether the mapping data is updatable and output a mapping update request based on the determination, as taught by Pahwa et al., in order to confirm that the write operation completed successfully before updating the mapping. Updating the mapping if the write operation didn’t complete successfully or if the data was still stored in the buffer area that was released could cause confusion or incorrect data reads.
Claims 11 and 19 recite similar limitations to claim 1 and would be rejected using the same rationale.
As to claim 4, Jeong and Pawha also disclose the storage controller of claim 1, wherein the metadata processing module is further configured to output a mapping update response indicating that the mapping data has been updated (see Jeong et al., para. 151 and 174, where when a write command is completed, the memory device may issue a response to notify of a completion . See para. 140-142, where the map update is only performed after the program operation is complete, and if a map update is requested before a valid page is copied, the map update cannot take place yet. Therefore, when a write command completion is sent, it would also indicate that the mapping table has been updated).
Claims 2-3, 5-10, 12-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong, in view of Pahwa et al. and in view of Fargeix et al. (U.S. Patent Application Publication No. 2025/0173265), herein referred to as Fargeix et al.
As to claim 2, Jeong and Pahwa et al. disclose the claimed invention except for the storage controller of claim 1, wherein the cache processing module is further configured to check a data hazard in response to the cache update request and output the cache update response based on a result of checking the data hazard.
However, Fargeix et al. discloses wherein the cache processing module is further configured to check a data hazard in response to the cache update request and output the cache update response based on a result of checking the data hazard (see para. 32-34, where data hazards are detected in memory accesses for a write after write by comparing address information of a target address with another address to determine if they match and are directed toward the same address. See para. 66 where memory access instructions are guaranteed to be committed depending on passing data hazard checks).
Jeong and Fargeix et al. are analogous art because they are from the same field of endeavor of memory accessing (see Jeong, abstract, and Fargeix et al., abstract, regarding memory accessing).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong to comprise wherein the cache processing module is further configured to check a data hazard in response to the cache update request and output the cache update response based on a result of checking the data hazard., as taught by Fargeix et al., in order to avoid executing instructions out of order. Checking for data hazards and correct instruction ordering is well known in the art and would be obvious to implement with Jeong.
Claim 12 recites similar limitations to claim 2 and would be rejected using the same rationale.
As to claim 3, Jeong, Pahwa et al., and Fargeix et al. also disclose the storage controller of claim 2, wherein the cache processing module is further configured to: receive a first write command and a second write command, the second write command being received after the first write command, and check the data hazard by comparing a logical address of the first write command to a logical address of the second write command (see Fargeix et al., para. 32-34, where data hazards are detected in memory accesses for a write after write by comparing address information of a target address with another address to determine if they match and are directed toward the same address).
Claim 13 recites similar limitations to claim 3 and would be rejected using the same rationale.
As to claim 5, Jeong and Pahwa et al. disclose the claimed invention except for the storage controller of claim 1, further comprising a read processing module configured to receive a read command from the cache processing module, and control a pending list comprising pending data, wherein the pending data comprises a logical address of the mapping data which has not been updated.
However, Fargeix et al. discloses the storage controller of claim 1, further comprising a read processing module configured to receive a read command from the cache processing module, and control a pending list comprising pending data, wherein the pending data comprises a logical address of the mapping data which has not been updated (see para. 125, where pending load/store operations may be queued and tracked. Although logical addresses are not specifically mentioned, Jeong tracks logical addresses, so the combination would allow for pending data to comprise a logical address of mapping data which has not been updated. Also see para. 68, where region mappings are tracked for address regions still to be committed).
Jeong and Fargeix et al. are analogous art because they are from the same field of endeavor of memory accessing (see Jeong, abstract, and Fargeix et al., abstract, regarding memory accessing).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong to comprise the storage controller of claim 1, further comprising a read processing module configured to receive a read command from the cache processing module, and control a pending list comprising pending data, wherein the pending data comprises a logical address of the mapping data which has not been updated, as taught by Fargeix et al., in order to avoid executing instructions out of order. Checking for data hazards and correct instruction ordering is well known in the art and would be obvious to implement with Jeong.
As to claim 6, Jeong, Pahwa et al. and Fargeix et al. also disclose the storage controller of claim 5, wherein the read processing module is further configured to receive, from the write post-processing module, an update check response indicating whether the mapping data has been updated (see Jeong, para. 151 and 174, where when a write command is completed, the memory device may issue a response to notify of a completion . See para. 140-142, where the map update is only performed after the program operation is complete, and if a map update is requested before a valid page is copied, the map update cannot take place yet. Therefore, when a write command completion is sent, it would also indicate that the mapping table has been updated).
As to claim 7, Jeong, Pahwa et al. and Fargeix et al. also disclose the storage controller of claim 6, wherein the read processing module is further configured to perform a read operation, based on the read command and the update check response (see Fargeix et al., para. 34, where data hazards are checked in a read after write. Therefore a read command that is directed toward the same address as a previous write command would need to wait for the write command to finish).
As to claim 8, Jeong, Pahwa et al. and Fargeix et al. also disclose the storage controller of claim 6, wherein the update check response comprises an incomplete response, wherein the incomplete response comprises the logical address of the mapping data which has not been updated (see para. Fargeix, para. 125, where pending load/store operations may be queued and tracked. Although logical addresses are not specifically mentioned, Jeong tracks logical addresses, so the combination would allow for pending data to comprise a logical address of mapping data which has not been updated. Also see para. 68, where region mappings are tracked for address regions still to be committed. Also see fig. 7b, step 424, where it is checked if an earlier instruction has been completed. If the earlier instruction has not completed, then that would constitute an incomplete response and the mapping data also would not be updated, as the map data is updated when the instruction completes as taught by Jeong, 140-142), and wherein the read processing module is further configured to add the read command to the pending data when a logical address of the read command is the same as a logical address of the incomplete response (see Fargeix et al. para. 34-35, where if there is a data hazard after comparing addresses, the memory access may be stalled in a load/store queue).
As to claim 9, Jeong, Pahwa et al. and Fargeix et al. also disclose the storage controller of claim 6, wherein the update check response comprises a complete response, the complete response comprising a logical address of the mapping data which has been updated (see para. Fargeix, para. 125, where pending load/store operations may be queued and tracked. Although logical addresses are not specifically mentioned, Jeong tracks logical addresses, so the combination would allow for pending data to comprise a logical address of mapping data which has not been updated. Also see para. 68, where region mappings are tracked for address regions still to be committed. Also see fig. 7b, step 424, where it is checked if an earlier instruction has been completed. When the instruction completes, that would constitute a complete response and therefore the map data updated when the instruction completes as taught by Jeong, 140-142), and wherein the read processing module is further configured to, when a logical address of at least one piece of pending data is the same as a logical address of the complete response, fetch the at least one piece of pending data (see Fargeix, para. 34-35, where there is an ordering requirement for certain commands, and the command may be executed after a previous command. Therefore, in a case of read after write, the read instruction would be processed and the piece of pending data fetched after the write instruction completes. Also see fig. 7b, step 422, 424 and 426, where it is checked if the earlier instruction has been completed, and performs the instruction as soon as the earlier instruction is completed).
As to claim 10, Jeong, Pahwa et al. and Fargeix et al. also disclose the storage controller of claim 9, wherein the read processing module is further configured to delete the at least one piece of pending data from the pending list (see Jeong, para. 56, describing a submission queue where new commands are added and then previous values may be overwritten. Also see Fargeix et al., para. 35, where memory accesses are added to a load/store queue and stalled until they are ready to be executed. The commands would be removed/deleted after executed).
As to claim 14, Jeong and Pahwa et al. disclose the claimed invention except for the operating method of claim 11, further comprising performing a read operation in response to receiving a read command, and wherein the performing of the read operation comprises controlling a pending list, the pending list comprising pending data for determining whether to suspend the read operation according to the read command.
However, Fargeix et al. disclose performing a read operation in response to receiving a read command, and wherein the performing of the read operation comprises controlling a pending list, the pending list comprising pending data for determining whether to suspend the read operation according to the read command (see para. 125, where pending load/store operations may be queued and tracked. Although logical addresses are not specifically mentioned, Jeong tracks logical addresses, so the combination would allow for pending data to comprise a logical address of mapping data which has not been updated. Also see para. 68, where region mappings are tracked for address regions still to be committed. Also see para. 34-35, where a read operation may be stalled/suspended in a load/store queue while waiting for a previous operation to complete in order to avoid a data hazard).
Jeong and Fargeix et al. are analogous art because they are from the same field of endeavor of memory accessing (see Jeong, abstract, and Fargeix et al., abstract, regarding memory accessing).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong to comprise the storage controller of claim 1, further comprising performing a read operation in response to receiving a read command, and wherein the performing of the read operation comprises controlling a pending list, the pending list comprising pending data for determining whether to suspend the read operation according to the read command, as taught by Fargeix et al., in order to avoid executing instructions out of order. Checking for data hazards and correct instruction ordering is well known in the art and would be obvious to implement with Jeong.
As to claim 15, Jeong, Pahwa et al. and Fargeix et al. also disclose the operating method of claim 14, wherein the performing of the read operation further comprises receiving an update check response indicating whether the mapping data has been updated (see Jeong, para. 151 and 174, where when a write command is completed, the memory device may issue a response to notify of a completion . See para. 140-142, where the map update is only performed after the program operation is complete, and if a map update is requested before a valid page is copied, the map update cannot take place yet. Therefore, when a write command completion is sent, it would also indicate that the mapping table has been updated).
As to claim 16, Jeong, Pahwa et al. and Fargeix et al. also disclose the operating method of claim 15, wherein the update check response comprises an incomplete response, the incomplete response comprising a logical address of the mapping data which has not been updated (see para. Fargeix, para. 125, where pending load/store operations may be queued and tracked. Although logical addresses are not specifically mentioned, Jeong tracks logical addresses, so the combination would allow for pending data to comprise a logical address of mapping data which has not been updated. Also see para. 68, where region mappings are tracked for address regions still to be committed. Also see fig. 7b, step 424, where it is checked if an earlier instruction has been completed. If the earlier instruction has not completed, then that would constitute an incomplete response and the mapping data also would not be updated, as the map data is updated when the instruction completes as taught by Jeong, 140-142), and wherein the controlling of the pending list comprises adding the read command to the pending data when a logical address of the read command is the same as a logical address of the incomplete response (see Fargeix et al. para. 34-35, where if there is a data hazard after comparing addresses, the memory access may be stalled in a load/store queue).
As to claim 17, Jeong, Pahwa et al. and Fargeix et al. also disclose the operating method of claim 15, wherein the update check response comprises a complete response, the complete response comprising a logical address of the mapping data which has been updated (see para. Fargeix, para. 125, where pending load/store operations may be queued and tracked. Although logical addresses are not specifically mentioned, Jeong tracks logical addresses, so the combination would allow for pending data to comprise a logical address of mapping data which has not been updated. Also see para. 68, where region mappings are tracked for address regions still to be committed. Also see fig. 7b, step 424, where it is checked if an earlier instruction has been completed. When the instruction completes, that would constitute a complete response and therefore the map data updated when the instruction completes as taught by Jeong, 140-142), and wherein the controlling of the pending list comprises, when a logical address of at least one piece of pending data is the same as a logical address of the complete response, fetching the at least one piece of pending data (see Fargeix, para. 34-35, where there is an ordering requirement for certain commands, and the command may be executed after a previous command. Therefore, in a case of read after write, the read instruction would be processed and the piece of pending data fetched after the write instruction completes. Also see fig. 7b, step 422, 424 and 426, where it is checked if the earlier instruction has been completed, and performs the instruction as soon as the earlier instruction is completed).
As to claim 18, Jeong, Pahwa et al. and Fargeix et al. also disclose the operating method of claim 17, wherein the controlling of the pending list comprises deleting the at least one piece of pending data from the pending list (see Jeong, para. 56, describing a submission queue where new commands are added and then previous values may be overwritten. Also see Fargeix et al., para. 35, where memory accesses are added to a load/store queue and stalled until they are ready to be executed. The commands would be removed/deleted after executed).
As to claim 20, Jeong and Pahwa et al. disclose the claimed invention except for the storage device of claim 19, wherein the controller is further configured to: control a pending list comprising pending data based on an update check response, wherein the pending data comprises a logical address of the mapping data which has not been updated, and wherein the update check response indicates whether the mapping data has been updated, and fetch at least one piece of pending data when a logical address of the at least one piece of pending data is same as a logical address of a complete response, wherein the complete response comprises a logical address of the mapping data which has been updated.
However, Fargeix et al. disclose wherein the controller is further configured to: control a pending list comprising pending data based on an update check response, wherein the pending data comprises a logical address of the mapping data which has not been updated (see para. 125, where pending load/store operations may be queued and tracked. Although logical addresses are not specifically mentioned, Jeong tracks logical addresses, so the combination would allow for pending data to comprise a logical address of mapping data which has not been updated. Also see para. 68, where region mappings are tracked for address regions still to be committed), and wherein the update check response indicates whether the mapping data has been updated, and fetch at least one piece of pending data when a logical address of the at least one piece of pending data is same as a logical address of a complete response, wherein the complete response comprises a logical address of the mapping data which has been updated (Also see fig. 7b, step 424, where it is checked if an earlier instruction has been completed, and performs the instruction as soon as the earlier instruction has completed. When the instruction completes, that would constitute a complete response and therefore the map data updated when the instruction completes as taught by Jeong, 140-142. Also see para. 34-35, where there is an ordering requirement for certain commands, and the command may be executed after a previous command. Therefore, in a case of read after write, the read instruction would be processed and the piece of pending data fetched after the write instruction completes).
Jeong and Fargeix et al. are analogous art because they are from the same field of endeavor of memory accessing (see Jeong, abstract, and Fargeix et al., abstract, regarding memory accessing).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong to comprise the storage controller of claim 1, further comprising performing a read operation in response to receiving a read command, and wherein the performing of the read operation comprises controlling a pending list, the pending list comprising pending data for determining whether to suspend the read operation according to the read command, as taught by Fargeix et al., in order to avoid executing instructions out of order. Checking for data hazards and correct instruction ordering is well known in the art and would be obvious to implement with Jeong.
Response to Arguments
Applicant’s arguments, filed 4/13/26, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Pahwa et al., which teaches where the mapping of memory addresses may happen after releasing the data in the buffer. Pahwa et al. is being combined with Jeong, which teaches the mapping of memory addresses involves the steps of determining whether the mapping data is updateable and outputting a mapping update request and mapping the addresses. Therefore, when combined, the combination would teach releasing data in the buffer and then subsequently determining whether the mapping data is updateable and outputting a mapping update request and mapping the addresses.
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 stand rejected.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
b. DIRECTION OF FUTURE CORRESPONDENCES
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/A.O/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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