DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed at the Korean Intellectual Property Office on March 21, 2024. It is noted, however, that applicant has not filed a certified copy of the 10-2024-0039288 application as required by 37 CFR 1.55.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “format conversion circuit,” quantization circuit,” and “input element scaling circuit” in claim 1, as well as “differential computation circuit,” quantization circuit,” “input element scaling circuit,” “power scaling circuit,” and “accumulation circuit” in claim 9.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
The format conversion circuit is being interpreted to correspond to the format conversion circuit shown in fig. 4 and described in pars. 52-59.
The quantization circuit is being interpreted to correspond to the quantization circuit DCCa shown in fig. 5 and described in pars. 68-75.
The input element scaling circuit is being interpreted to correspond to the input scaling circuit DCCb shown in fig. 5 and described in pars. 68-76.
The differential computing circuit is being interpreted to correspond to the differential computation circuit DCC shown in fig. 5 and described in pars. 68-76.
The power scaling circuit is being interpreted to correspond to the power scaling circuit DCCb_1 shown in fig. 10 and described in pars. 93-96.
The accumulation circuit is being interpreted to correspond to the accumulation circuit DCCb_2 shown in fig. 10 and described in pars. 93 and 97.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the plurality of weights" in lines 9-10. There is insufficient antecedent basis for this limitation in the claim. The examiner is interpreting this to refer to the “plurality of differential weights” in lines 2-3.
Claims 2-8 depend from independent claim 1 and do not resolve the deficiencies of the parent claim, and are similarly rejected.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis
Claims 1-20 are within the four statutory categories. Claims 1-8 are directed towards a memory device, which is within the four statutory categories (i.e. machine). Claims 9-17 are directed towards a differential computation circuit, which is within the four statutory categories (i.e. machine). Claims 18-20 are directed towards an operation method of a memory device, which is within the four statutory categories (i.e. process)
Step 2A Prong 1
Claim 1 recites an abstract idea (mental process):
“generate a plurality of differential weights based on a plurality of weights provided from an external device;”
“generate a plurality of scale coefficients based on the plurality of differential weights;”
“provide a plurality of output elements corresponding to products of the first input element with each of the plurality of weights to the external device based on the plurality of scale coefficients.”
Generating the differential weights is simple arithmetic, and may be done in the human mind, and/or with the aid of pen and paper. Applicant’s figure 4 shows the generation of the differential weights, which is done by subtracting one number from another.
Generating the scale coefficients is also simple arithmetic, and may be done in the human mind, and/or with the aid of pen and paper. Par. 80 describes generating the scale coefficients “by quantizing amplitudes of the 0-th to n-th differential weights DW0-DWN respectively. For example, the quantization circuit DCCa may quantize the amplitude of each of the 0-th to n-th differential weights DW0-DWn in a form of 2N (wherein the N is an integer).” In other words, it’s simply multiplication.
Generating the scale coefficients is also simple arithmetic, and may be done in the human mind, and/or with the aid of pen and paper. This is described in par. 24, “In operation S230, the memory device 100 may generate the plurality of output elements OE corresponding to the products of the input element IE and the plurality of differential weights DW. For example, the internal processor 111 may generate the 0-th to n-th output elements OE0-OEn based on the input element IE and the 0-th to n-th differential weights DW0-DWn.” This is simply a multiplication operation.
Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2
With respect to the additional elements of claim 1:
“a memory cell array configured to store a first input element provided from the external device and to store the plurality of differential weights” is a type of insignificant extra-solution activity (mere data gathering) in a generic computing environment of a memory cell array storing data.
The claim recited generic computing elements in the form of “a memory device,” “a format conversion circuit,” “a quantization circuit” and an “input element scaling circuit.”
Step 2B
With respect to storing input elements provided form the external device and storing the plurality of differential weights described above as insignificant extra-solution activities, these limitations are well-understood, routine or conventional (see MPEP 2106.05(d)(II) – storing and retrieving information in memory). The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Step 2A Prong 1
Claim 9 recites an abstract idea (mental process):
“generate 0-th to n-th scale coefficients based on 0-th to n-th differential weights (wherein n is an integer greater than or equal to 1);”
“generate 0-th to n-th output elements based on the 0-th to n-th scale coefficients and an input element;”
“generate 0-th to n-th differentially scaled input elements by scaling the input element based on the 0-th to n-th scale coefficients.”
“generating the 0-th to n-th output elements by sequentially accumulating the 0-th to n-th differentially scaled input elments.”
Generating the scale coefficients, generating the differentially scaled input elements and generating the output elements are all examples of simple arithmetic, and may be done in the human mind, and/or with the aid of pen and paper. Applicant’s figure 4, par. 24, and par. 80 describe the arithmetic operations for generating these values, as discussed above in the rejection of claim 1.
Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2
With respect to the additional elements of claim 9:
The claim recited generic computing elements in the form of “differential computation circuit,” “a quantization circuit,” “an input element scaling circuit,” “a power scaling circuit,” and “an accumulation circuit.”
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B
As the claims only contains generic computing elements in addition to the abstract idea, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Step 2A Prong 1
Claim 18 recites an abstract idea (mental process):
“generating, based on 0-th and first differentially scaled input elements respectively corresponding to products of the first input element with the 0-th and first differential weights, 0-th and first output elements respectively corresponding to products of the first input element with the 0th and first weights, in response to the weight multiplication command.”
generating the output elements the output elements as described is simple arithmetic, and may be done in the human mind, and/or with the aid of pen and paper. Applicant’s figure 4, par. 24, and par. 80 describe the arithmetic operations for generating these values, as discussed above in the rejection of claim 1.
Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2
With respect to the additional elements of claim 18:
“storing 0-th and first differential weights generated based on 0-th and first weights provided from an external device” is a type of insignificant extra-solution activity (mere data gathering) in a generic computing environment of a memory storing data.
“receiving a first input element from the external device” is a type of insignificant extra-solution activity (mere data gathering) in a generic computing environment.
“receiving a weight multiplication command for the 0-th and first weights and the first input element from the external device” is a type of insignificant extra-solution activity (mere data gathering) in a generic computing environment.
“outputting the 0-th and first output elements to the external device” is a type of insignificant extra-solution activity in a generic computing environment.
The claim recited generic computing elements in the form of “a memory device.”
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B
With respect to storing input elements provided form the external device, receiving inputs and a weight multiplication command, and outputting output elements described above as insignificant extra-solution activities, these limitations are well-understood, routine or conventional (see MPEP 2106.05(d)(II) – storing and retrieving information in memory). The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
The dependent claims 2-8, 10-17 and 19-20 depend from one of the independent claims 1, 9 or 17, and are directed to the same abstract idea(s) of their respective parent claim. Accordingly the claims are directed to an abstract idea. The claims describe generating values using mathematics, that are part of the abstract idea. The dependent claims also describe generic computing elements such as “a power scaling circuit,” “an accumulation circuit,” “an output register,” and “a storage format managing circuit.” None of the dependent claims include additional elements that are sufficient to amount to significantly more than the judicial exception.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jeon et al., US PGPub 2025/0139193 teaches scale coefficients. Tran et al., US PGPub 2024/0282351 and Tran et al., US PGPub 2024/0256846 teach differential weights. Shin et al., US PGPub 2023/0206052 teaches differential weights and an accumulator. Flamant, US Patent 11,106,976 teaches a neural network for machine learning using differential weights. Lee et al., US PGPub 2020/0372340 teaches differential weights and floating point numbers. Nicol et al., US PGPub 2019/0279086 teaches deep learning using differential weights. CN 110209375 teaches differential weight storage and a multiply-accumulate circuit. Bayat et al., US PGPub 2017/0337466 teaches a deep learning neural network.
With respect to independent claim 1, the closest prior art, CN 110209375, teaches “a memory device comprising: a format conversion circuit configured to generate a plurality of weights based on a plurality of weights provided from an external device; a memory cell array configured to store a first input element provided from the external device and to store the plurality of differential weights,” in the abstract. Additionally, Jeon teaches “a quantization circuit configured to generate a plurality of scale coefficients based on the plurality of different weights,” in par. 84, with the exception that Jeon uses pure weights and not differential weights, and therefore the combination of CN 110209375 with Jeon, along with the rest of the cited prior art fails to teach “a quantization circuit configured to generate a plurality of scale coefficients based on the plurality of differential weights; and an input element scaling circuit configured to provide a plurality of output elements corresponding to products of the first input element with each of the plurality of weights to the external device based on the plurality of scale coefficients.”
Similarly, with respect to independent claim 9, since CN 110209375 and Jeon fail to teach the particular combination of scale coefficients based on differential weights, the cited prior art fails to teach “a quantization circuit configured to generate 0-th to n-th scale coefficients based on 0-th to n-th differential weights (wherein n is an integer greater than or equal to 1); and an input element scaling circuit configured to generate 0-th to n-th output elements based on the 0-th to n-th scale coefficients and an input element, wherein the input element scaling circuit comprises, a power scaling circuit configured to generate 0-th to n-th differentially scaled input elements by scaling the input element based on the 0-th to n-th scale coefficients, and an accumulation circuit configured to sequentially generate the 0-th to n-th output elements by sequentially accumulating the 0-th to n-th differentially scaled input elements.”
Finally, with respect to independent claim 18, CN 110209385 teaches “an operation method of a memory device, comprising: storing 0-th and first differential weights generated based on 0-th and first weights provided from an external device; receiving a first input element from the external device,” in the abstract. CN 110209385 and the other prior art of record fails to teach “receiving a weight multiplication command for the 0-th and first weights and the first input element from the external device; generating, based on 0-th and first differentially scaled input elements respectively corresponding to products of the first input element with the 0-th and first differential weights, 0-th and first output elements respectively corresponding to products of the first input element with the 0-th and first weights, in response to the weight multiplication command; and outputting the 0-th and first output elements to the external device.”
The remaining claims depend from the above independent claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN DARE whose telephone number is (571)272-4069. The examiner can normally be reached M-F 9:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132