DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the amendment filed by Applicant on 07/08/2026. This action is made FINAL.
Claim Rejections - 35 USC § 112
The 35 U.S.C. 112(b) rejections have been withdrawn in response to the amendments submitted by the Applicant.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 10, 12, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Qing et al (Publication number: US 2017/0154565) in view of Hong et al (Publication number: US 2022/0093028).
Consider Claim 1, Qing et al shows a gate driving circuit (see figure 7), comprising:
(a) A set node (see figure 4; and paragraphs 39-42); (The set node is read as the PU node).
(b) A second controller configured to control a voltage of a reset node (The reset node is read as the PD node. The output unit outputs the output signal Out(n) through the output terminal of the shift register in response to the low level first control signal CK, and the pull-down control unit sets the pull-down node PD in response to the low level second control signal CKB).
(c) A first output transistor connected to the set node (see figure 4); (T1 is read as the first output transistor).
(d) A second output transistor connected to the reset node (see figure 4); (T2 is read as the second output transistor).
However, Qing et al does not specifically show a controller configured to control voltage of a set node, wherein the first output transistor is configured to output a gate low voltage to an output terminal in response to the voltage of the set node; and the second output transistor is configured to output a gate high voltage to the output terminal in response to the voltage of the reset node.
In the same field of endeavor, Hong et al shows a controller configured to control voltage of a set node, wherein the first output transistor is configured to output a gate low voltage to an output terminal in response to the voltage of the set node; and the second output transistor is configured to output a gate high voltage to the output terminal in response to the voltage of the reset node (see figure 4; and paragraphs 62-68); (The first discharging portion 20 may discharge the Q node with the first gate-off voltage VGL of the second power terminal 6 in response to control of a QB node. The first discharging portion 20 may include a Q discharging transistor T3 in which a gate electrode is connected to the QB node, a source electrode is connected to the second power terminal 6 and a drain electrode is connected to the Q node. The Q discharging transistor T3 may be turned on when the QB node is high logic, thereby discharging the Q node with the first gate-off voltage VGL).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the output portion of Hong et al into the driving circuit of Qing et al in order to minimize leakage (see Hong et al; paragraphs 4-8).
Consider Claim 10, Qing et al shows a gate driving circuit (see figure 7), comprising:
(a) A set node (see figure 4; and paragraphs 39-42); (The set node is read as the PU node).
(b) A second controller configured to control a voltage of a reset node; a first reset transistor connected between a gate high voltage line and a second node (The reset node is read as the PD node. The output unit outputs the output signal Out(n) through the output terminal of the shift register in response to the low level first control signal CK, and the pull-down control unit sets the pull-down node PD in response to the low level second control signal CKB).
(c) A first output transistor connected to the set node (see figure 4); (T1 is read as the first output transistor).
(d) A second output transistor connected to the reset node (see figure 4); (T2 is read as the second output transistor).
However, Qing et al does not specifically show a controller configured to control voltage of a set node, wherein the first output transistor is configured to output a gate low voltage to an output terminal in response to the voltage of the set node; and the second output transistor is configured to output a gate high voltage to the output terminal in response to the voltage of the reset node.
In the same field of endeavor, Hong et al shows a controller configured to control voltage of a set node, wherein the first output transistor is configured to output a gate low voltage to an output terminal in response to the voltage of the set node; and the second output transistor is configured to output a gate high voltage to the output terminal in response to the voltage of the reset node (see figure 4; and paragraphs 62-68); (The first discharging portion 20 may discharge the Q node with the first gate-off voltage VGL of the second power terminal 6 in response to control of a QB node. The first discharging portion 20 may include a Q discharging transistor T3 in which a gate electrode is connected to the QB node, a source electrode is connected to the second power terminal 6 and a drain electrode is connected to the Q node. The Q discharging transistor T3 may be turned on when the QB node is high logic, thereby discharging the Q node with the first gate-off voltage VGL).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the output portion of Hong et al into the driving circuit of Qing et al in order to minimize leakage (see Hong et al; paragraphs 4-8).
Consider Claims 4 and 15, Hong et al shows that a first transistor configured to provide a start signal or an output signal of a previous stage to a second node in response to a clock signal; and a transfer transistor configured to transfer a voltage of the second node to the set node in response to the gate low voltage (see paragraphs 93-96); (The first charging portion 10A may include a pair of Q charging transistors T1 having gate electrodes commonly connected to the set terminal 2, serially connected between the set terminal 2 and the Q node. The pair of Q charging transistors T1 are turned on when the start signal VST or the carry signal CRn−4 of the preceding stage is high logic, thereby pre-charging the Q node. The carry signal CRn−4 of the preceding stage means a carry signal output through the carry terminal of the (n−4)th preceding stage).
Consider Claims 5 and 16, Qing et al shows that the first controller controls the voltage of the set node in response to a clock signal and a start signal, or the clock signal and an output signal of a previous stage (see figure 7; and paragraphs 50-52); (The STV signal is read as the start signal. Further, Qing et al states that the signal CK is used as the first control signal, and that when CN is of high level while CNB is of low level, an output signal of a former-stage of shift register is used as a set signal for a latter-stage of shift register, while an output signal of the latter-stage of shift register is used as a reset signal of the former-stage of shift register).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Qing et al (Publication number: US 2017/0154565) in view of Hong et al in view of Feng et al (Publication number: US 2022/0051618).
Consider Claim 12, Qing et al in view of Hong et al do not specifically show that the reset signal is a signal opposite in phase with respect to a start signal and delayed by a predetermined period of time with respect to the start signal.
In related art, Feng et al shows that the reset signal is a signal opposite in phase with respect to a start signal and delayed by a predetermined period of time with respect to the start signal (see paragraphs 146-148).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Feng et al into the teaching of Qing et al and Hong et al in order to prevent an electrical signal to remain on a node within duration of the current frame (see Feng et al; paragraphs 146-148).
Allowable Subject Matter
Claims 6-9, 17-20, and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MICHAEL A FARAGALLA/Primary Examiner, Art Unit 2624 10/02/2026
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