DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
This Office Action is responsive to amendment filed on 05/12/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-17, and 19-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2014/0149631, previously cited) in view of Oh (US 2009/0063786).
Regarding claim 1, Kim teaches an apparatus (figs. 2 and 3) comprising first memory device (111) comprising a buffer (1160) or cache for a second memory device (121, [0047]-[0050], buffer 1160 is used for receiving data from the second memory device 121 via 182-183. Therefore, buffer 1160 is considered as buffer for the second memory device); wherein the buffer or cache of the first memory device operates as the buffer or cache of the second memory device (buffers 1160 and 1250 are working in conjunction with each other to transfer data between the first memory device (111) and the second memory device (121). The buffer 1160 stores data from the second memory device 121 via the buffer 1250. Therefore, the buffer 1160 in conjunction with the buffer 1250 operates as the buffer for the second memory device ([0050]). Note that, the claim does not call for the second memory device not to have a buffer or cache.); and a set of pins (181-188) configured to couple the first memory device to the second memory device ([0038]-[0050]).
Kim further teaches a controller (20) configured to communicate with the memory device ([0035]) but silent to configure the memory device as claimed.
However, Oh teaches daisy chain memory configuration apparatus comprises a first memory device (110-1) comprising a buffer or cache for a second memory device (110-2), wherein the buffer or cache of the first memory device operates as the buffer or cache of the second memory device; and wherein the buffer or cache of the first memory device operates as the buffer or cache of the second memory device is configured by a processor or controller (102) that external to the apparatus (fig. 1A, 2, [0037]-[0040], [0044], [0046], [0047] and [0055]).
In view of Oh’s teaching, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim by incorporating the teaching as taught by Oh in order to arrive at the claimed invention.
Regarding claim 2, Kim as modified by Oh teaches all subject matter claimed as applied above. Kim further teaches wherein the set of pins comprises a first set of pins (182-183), and further wherein the apparatus comprises a third memory device (131) connected to the first memory device via a second set of pins (184-185).
Regarding claim 3, Kim as modified by Oh teaches all subject matter claimed as applied above. Oh further teaches wherein the third memory device comprises a controller (125, fig. 1A and [0034]).
Regarding claim 4, Kim as modified by Oh teaches all subject matter claimed as applied above. Kim further teaches wherein the buffer or cache comprises a buffer (DBU, fig. 3), and wherein a size and location of the buffer is configured by a processor chip or memory controller (MC 20, figs. 1 and 2).
Regarding claim 5, Kim as modified by Oh teaches all subject matter claimed as applied above. Kim further teaches wherein the processor chip or memory controller is not part of the first memory device (fig. 2).
Regarding claim 6, Kim as modified by Oh teaches all subject matter claimed as applied above. Kim further teaches wherein the buffer is configured by the processor chip or memory controller based on signals sent from the processor chip or memory controller to the first memory device indirectly by way of a third memory device (fig. 2 and [0039]-[0043]).
Regarding claim 7, Kim as modified by Oh teaches all subject matter claimed as applied above. Kim further teaches wherein the third memory device is connected to the first memory device via a second set of pins (fig. 2).
Regarding claim 8, Kim as modified by Oh teaches all subject matter claimed as applied above. Kim further teaches wherein the third memory device comprises a cache for the first memory device (figs. 2 and 3).
Regarding claim 9, Kim as modified by Oh teaches all subject matter claimed as applied above. Kim further teaches wherein the buffer or cache comprises a cache, and further wherein the second memory device comprises a buffer for a third memory device (131, fig. 2).
Regarding claim 10, Kim as modified by Oh teaches all subject matter claimed as applied above. Kim further teaches wherein the third memory device is connected to the first memory device via a second set of pins (184, fig. 2).
Regarding claim 11, Kim as modified by Oh teaches all subject matter claimed as applied above. Oh further teaches wherein the buffer or cache comprises a buffer, wherein the first memory device comprises non-volatile random-access memory, and wherein the second memory device comprises flash memory (fig. 2, [0060] and [0091]).
Regarding claim 12, Kim as modified by Oh teaches all subject matter claimed as applied above. Oh further teaches wherein the buffer or cache comprises a cache, wherein the first memory device comprises dynamic random-access memory, and wherein the second memory device comprises non-volatile random-access memory (fig. 2, [0036] and [0091]).
Regarding claim 13, Kim teaches an apparatus comprising: a first memory device (111) comprising a cache for a second memory device (121, [0050], buffer 1160 is used for receiving data from the second memory device 121 via 182-183. Therefore, buffer 1160 is considered as buffer for the second memory device as claimed); a first set of pins (182-183) configured to couple the first memory device to the second memory device; the second memory device comprises a buffer for a third memory device (131); wherein the buffer of the second memory device operates as the buffer of the third memory device (same rationale is applied for claim 1 above and also see [0058]); and a second set of pins (184-185) configured to couple the second memory device to the third memory device (figs. 2 and 3).
Kim further teaches a controller (20) configured to communicate with the memory devices ([0035]) but silent to configure the memory device as claimed.
However, Oh teaches daisy chain memory configuration apparatus comprises a first memory device (110-1) comprising a buffer or cache for a second memory device (110-2), wherein the buffer or cache of the first memory device operates as the buffer or cache of the second memory device; and wherein the buffer or cache of the first memory device operates as the buffer or cache of the second memory device is configured by a processor or controller (102) that external to the apparatus (fig. 1A, 2, [0037]-[0040], [0044], [0046], [0047] and [0055]).
In view of Oh’s teaching, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim by incorporating the teaching as taught by Oh in order to arrive at the claimed invention.
Regarding claim 14, Kim as modified by Oh teaches all subject matter claimed as applied above. Kim further teaches wherein the first memory device is connected to a processor or a memory controller (MC 20), and wherein the processor or the memory controller controls each of the first memory device, second memory device, and third memory device (fig. 2, [0035] and [0040]-[0043]).
Regarding claim 15, Kim as modified by Oh teaches all subject matter claimed as applied above. Oh further teaches wherein the first memory device comprises dynamic random-access memory ([0036] and [0091]).
Regarding claim 16, Kim as modified by Oh teaches all subject matter claimed as applied above. Oh further teaches wherein the second memory device comprises non-volatile random-access memory ([0060]).
Regarding claim 17, Kim as modified by Oh teaches all subject matter claimed as applied above. Oh further teaches wherein the third memory device comprises flash memory ([0036]
Regarding claim 19, Kim teaches an apparatus (figs. 2 and 3) comprising: a first memory device (111); a second memory device (121) comprising a buffer (1250 and 1260) or cache for the first memory device or a third memory device (as shown in figure 3, data in buffer 1250 is to provide data to memory device 111 or data buffer 1260 is for receiving data from buffer in the third memory device 131, see also, [0047]-[0050] and [0058]); wherein the buffer or cache of the second memory device operates as the buffer or cache of the first memory device or the third memory device ((same rationale is applied for claim 1 above and also see [0058]); the third memory device (131); first wiring (172) configured to couple the first memory device to the second memory device; and a second wiring (173) configured to couple the second memory device to the third memory device ([0038]-[0050]).
Kim further teaches a controller (20) configured to communicate with the memory devices ([0035]) but silent to configure the memory device as claimed.
However, Oh teaches daisy chain memory configuration apparatus comprises a first memory device (110-1) comprising a buffer or cache for a second memory device (110-2), wherein the buffer or cache of the first memory device operates as the buffer or cache of the second memory device; and wherein the buffer or cache of the first memory device operates as the buffer or cache of the second memory device is configured by a processor or controller (102) that external to the apparatus (fig. 1A, 2, [0037]-[0040], [0044], [0046], [0047] and [0055]).
In view of Oh’s teaching, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim by incorporating the teaching as taught by Oh in order to arrive at the claimed invention.
Regarding claim 20, Kim as modified by Oh teaches all subject matter claimed as applied above. Kim further teaches a first group of memory devices (110) comprising first memory device (111) and a fourth memory device (114); a second group of memory devices (120) comprising the second memory device (121) and a fifth memory device (124); and a third group of memory devices (130) comprising the third memory device (131) and a sixth memory device (134); and wherein the first wiring connects each of the first memory device and the fourth memory device to the second memory device and the fifth memory device; and the second wiring connects each of the second memory device and the fifth memory device to the third memory device and the sixth memory device. (figs. 1, 2 and [0032]-[0040]).
Regarding claim 21, Kim as modified by Oh teaches all subject matter claimed as applied above. Oh further teaches wherein the processor or controller is further configured to set cache policy parameters (commands) of the buffer or cache based on a write of data by the processor or controller to the first memory device, wherein the buffer or cache comprises a cache ([0055] and [0104]).
Regarding claim 22, Kim as modified by Oh teaches all subject matter claimed as applied above. Oh further teaches wherein the first memory device comprises a cache for the second memory device, wherein the buffer or cache of the second memory device comprises a buffer for the third memory device, and wherein each of the cache for the second memory device and the buffer for the third memory device are configured by the processor or controller that is external to the apparatus (fig. 1A).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim as modified by Oh as applied to claim 13 above, and further in view of Tremaine (US 2011/0087834, cited by applicant).
Regarding claim 18, Kim as modified by Oh teaches all subject matter claimed as applied above but silent to a logical-to-physical mapping as claimed.
However, Tremaine teaches memory comprises a logical-to-physical mapping as claimed (fig. 4).
In view of Tremaine’s teaching, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Kim and Oh by incorporating the teaching as taught by Tremaine in order to arrive at the claimed invention.
Response to Arguments
Applicant’s arguments, see Remarks, filed 05/12/2026, with respect to the rejection(s) of claim(s) 1-22 under 35 U.S.C 102 & 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim, Oh and Tremaine.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tuyen Kim Vo whose telephone number is (571)270-1657. The examiner can normally be reached Mon-Thurs: 8AM-6:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Paik can be reached at 571-272-2404. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUYEN K VO/Primary Examiner, Art Unit 2876
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