DETAILED ACTION
This action is responsive to 09/09/2024.
Claims 1-18 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US Pub. 2023/0335595), hereinafter Chen, in view of Potera (US Patent 11,631,762).
Regarding claim 1, Chen discloses a method of manufacturing a transistor (see figs. 3A-3K), the method comprising: providing a substrate (substrate 300-see fig. 3A and [0039]); forming a drift layer on the substrate having a protruding portion (drift layer 302 has protruding portions-see fig. 3A and[0039]); implanting a well layer into the drift layer and into sides of the protruding portion of the drift layer (well regions 310-see fig. 3E and [0044]); forming a recess portion into the well layer (see, for example, fig. 3F); implanting a source layer into a portion of the recessed portion of the well layer and extending into an undercut in the well layer and into well layer along the sides of the protruding portion of the drift layer (a tilt implantation IMP2 is performed on the drift layer 302 to form a plurality of source regions 314 within the well regions 310-see fig. 3F and [0045]. The source regions extend into an undercut in the well regions 310 as illustrated in fig. 3F); forming an insulating layer over a portion of the source layer and over a portion of the well layer on the sides of the protruding portion of the drift layer (see fig. 3I with description in [0048]-a gate insulation layer 320 is formed on the drift layer 302 and the bottom 304b and the sidewalls 304a of each of the V-grooves 304); and forming a gate electrode over the insulating layer (forming a plurality of gates G on the gate insulation layer 320-see fig. 3J and [0049]).
Chen does not appear to expressly disclose implanting a JFET layer into the protruding portion in the drift layer.
Potera is relied upon to teach implanting a JFET layer into the protruding portion in the drift layer (see, for example, fig. 2 with description in [col. 4, ll. 34-35 and 42-47], which illustrates an epitaxial layer 35 that forms an extended drain or drift region of Sic MOSFET 25, wherein a JFET region 43 is formed at a vertical portion (protruding portion)o of the drift layer 35).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Potera with the invention of Chen by implanting a JFET layer into the protruding portion of the drift layer, as taught by Potera, in order to provide a SiC DMOSFET device structure with a JFET region having a specific doping profile that provides reduced sensitivity of JFET resistance, which is a significant portion of total specific on-resistance, to process variation affecting the width of the JFET region (see [col. 4, ll. 15-24]).
Regarding claim 10, Chen discloses a transistor (see fig. 2) comprising: a substrate (substrate 300-see fig. 3A and [0039]); a drift layer on the substrate, the drift layer having a protruding portion (drift layer 302 has protruding portions-see fig. 3A and[0039]); a well layer within the drift layer and within sides of the protruding portion of the drift layer (well regions 310-see fig. 3E and [0044]); a source layer within a portion of the well layer and extending into an undercut in the well layer and into the well layer along the sides of the protruding portion of the drift layer (a tilt implantation IMP2 is performed on the drift layer 302 to form a plurality of source regions 314 within the well regions 310-see fig. 3F and [0045]. The source regions extend into an undercut in the well regions 310 as illustrated in fig. 3F); an insulating layer over a portion of the source layer and over a portion of the well layer on the sides of the protruding portion of the drift layer (see fig. 3I with description in [0048]-a gate insulation layer 320 is formed on the drift layer 302 and the bottom 304b and the sidewalls 304a of each of the V-grooves 304); and a gate electrode over a portion of the insulating layer (forming a plurality of gates G on the gate insulation layer 320-see fig. 3J and [0049]).
Chen does not appear to expressly disclose a JFET layer within the protruding portion of the drift layer.
Potera is relied upon to teach a JFET layer within the protruding portion of the drift layer (see, for example, fig. 2 with description in [col. 4, ll. 34-35 and 42-47], which illustrates an epitaxial layer 35 that forms an extended drain or drift region of Sic MOSFET 25, wherein a JFET region 43 is formed at a vertical portion (protruding portion)o of the drift layer 35).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Potera with the invention of Chen by implanting a JFET layer into the protruding portion of the drift layer, as taught by Potera, in order to provide a SiC DMOSFET device structure with a JFET region having a specific doping profile that provides reduced sensitivity of JFET resistance, which is a significant portion of total specific on-resistance, to process variation affecting the width of the JFET region (see [col. 4, ll. 15-24]).
Regarding claims 2 and 11, Chen discloses that the substrate 300 is a silicon carbide (SiC) substrate and may be an n-type (first type) substrate (see fig. 3A and [0039]).
However, Chen is silent with regards to the doping concentration of the substrate.
Potera, in for example, fig. 2 with description in [col. 6, ll. 4-7], teaches that substrate 34 is an n+ SiC substrate with a concentration of about 4E18/cm3.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Potera with the invention of Chen by doping the SiC substrate of Chen with any reasonable concentration, such as that taught by Potera, which constitutes combining prior art element according to known methods to yield predictable results.
Regarding claims 3 and 12, Chen discloses wherein the drift layer comprises a second concentration of the first type dopant (drift layer 302 may be an N-drift layer, wherein the doping concentration of the drift layer 302 is ranged from 3E15/cm3 to 4E16/cm3)).
Chen is silent about the specific concentration of the substrate 300, therefore, Chen does not appear to expressly disclose the first concentration is greater than the second concentration.
Potera is further relied upon to each the first concentration is greater than the second concentration (see, for example, drift doping for JFET #3 having a device structure as shown in fig. 2 (see [col. 8, ll. 28-30]) is 1E16/cm3, which is lower than that of SiC substrate (4E18/cm3-see [col. 6, ll. 4-7])).
Regarding claims 4 and 13, Chen discloses wherein the well layer comprises a third concentration of a second type dopant (the well regions 310 may be p-type wells, and the doping concentration of the well region 106 is ranged from 4.2 E16/cm3 to 5.6E17/cm3-see [0044]).
Regarding claims 5 and 14, Chen discloses wherein the source layer comprises a fourth concentration of the first type dopant (the source regions 314 may be N+ regions, and the doping concentration of the plurality of source regions is ranged from 5E17/cm3 to 5E19/cm3-see [0045]).
Regarding claims 6 and 15, Potera is further relied upon to teach wherein the JFET layer comprises a fifth concentration of the first type dopant (see, for example, figs. 2 and 7-JFET region is n-type with a doping of 4.5E16/cm3)).
Regarding claims 7 and 16, Chen discloses wherein the insulating layer comprises polysilicon, oxide or a mixture of polysilicon and oxide (the gate insulation layer 320 may be a gate oxide-see [0048]).
Regarding claims 8 and 17, Chen discloses wherein the first type dopant comprises an n-type dopant and the second type dopant comprises a p-type dopant (see, for example, [0039]-substrate 300 and drift layer 302 are both n-type (first type dopant)).
Regarding claims 9 and 18, Chen does not appear to expressly disclose wherein the first type dopant comprises a p-type dopant and the second type dopant comprises an n-type dopant.
However, choosing the first type dopant to be a p-type dopant and the second type dopant to be an n-type dopant is an obvious design choice and simply constitutes choosing from a finite (two) number of identified, predictable solutions for selecting the first and the second type dopants, with a reasonable expectation of success.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARDIS F AZONGHA whose telephone number is (571)270-7706. The examiner can normally be reached 10AM-7:00PM.
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/SARDIS F AZONGHA/Primary Examiner, Art Unit 2627
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