Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 09/09/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: numeral 426 is described in Par. [0087] of the specification but is not present in the drawings. Figure 4 is described in paragraph [0087] and includes reference sign 426, but figure 4 does not show a numeral 426. Similarly, paragraph [0153] includes numeral 1582 but numeral 1582 does not appear in the drawings. Similarly, paragraph [0151] includes bottom dielectric layer pair 1029, but the drawings do not show a numeral 1029. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For claims 7 and 14, the claims state “…a core filling film in a center; a channel layer…”. The claims appear to omit a structural relationship, as the term “in a center” does not appear to relate back to another object. This makes it unclear if the “center” being referred to is the center of the memory strings, the center of the conductor/dielectric stack, the center of the device, or the center of some other layer or area of the memory device. This uncertainty results in multiple interpretations and results in the claim being indefinite. For the purpose of compact prosecution, examiner is interpreting claims 7 and 14 as stating “…a core filling film in a center of each of the plurality of memory strings…” as this interpretation appears to match the drawings and specification wherein the core filling film is shown in the center of the individual memory strings.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20190115358 A1 hereinafter Lee in further view of CN 11819691 A1 hereinafter Sun.
For claim 1, Lee teaches a three-dimensional memory device comprising: a bottom select gate (Lee, fig. 7G numeral 131); an alternating conductor/dielectric layer stack disposed over the bottom select gate in a vertical direction (fig. 7G numeral 130 and 140 shows alternating conductor and dielectric layers); a slit structure extending through the alternating conductor/dielectric layer stack and the bottom select gate in the vertical direction (fig. 7G numeral 160); and wherein the slit structure extends along a first direction perpendicular to the vertical direction (fig. 8 numeral 162). Lee also teaches the bottom gate includes a first portion extending along the first direction and a second portion extending along a second direction perpendicular to the first direction (fig. 8 numeral GS). Lee is silent regarding a bottom select gate cut extending through the bottom select gate in the vertical direction and the bottom select gate cut structure includes the second portion in contact with the slit structure.
Sun teaches a memory device including a slit structure (Sun, fig. 21 numeral 161-1 – 161-6) extending through the alternating conductor/dielectric layer stack (fig. 21 numeral 141 and 142e) and the bottom select gate (fig. 21 numeral 131-1, 132-1e) in a vertical direction and a bottom select gate cut structure extending through the bottom select gate in the vertical direction (fig. 21 numeral 136-1). The bottom select gate cut structure and the slit structure are shown to be in contact with each other in a second direction (fig. 21 and 22 direction Y) perpendicular to a first direction (fig. 21 direction X). Figure 22 also shows the bottom select gate cut 136-1 and 136-2 in contact with slit structures 161-1 – 161-6.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the bottom select gate cut structure in Sun with the slit structure in Lee in order to better isolate the bottom select gate portions by inserting dielectric material between portions of the bottom select gate.
For claim 2, Lee and Sun teach all of claim 1. Sun also teaches the bottom select gate includes a first bottom select gate segment and a second bottom select gate segment (Sun, fig. 22 numerals F-1 and F-2) disposed adjacent to the first bottom select gate segment in the second direction, wherein the bottom select gate cut structure is disposed between the first bottom select gate segment and the second bottom select gate segment (fig. 22 numeral 136-1 and 136-2).
For claim 3, Lee and Sun teach all of claim 2. Sun also teaches the first bottom select gate segment that has a size in the second direction (Sun, fig. 22 numeral F-1) that is greater than a size of the second bottom select gate segment in the second direction (fig. 22 numeral F-2; direction Y matches the second direction in figure 21).
For claim 4, Lee and Sun teach all of claim 2. Sun also teaches the first bottom select gate segment (Sun, fig. 22 numeral F-1) comprising: a first portion extending along the first direction (fig. 22 direction X); and a second portion extending from the first portion in the second direction (fig. 22 direction Y).
For claim 5, Lee and Sun teach all of claim 5. Lee also teaches the bottom select gate including a first bottom select gate segment comprising a first and second portion (Lee, fig. 8 numeral GS shows the first bottom select gate segment comprising multiple portions), and wherein a bottom select gate contact contacts the first and second portions of the first bottom select gate segment (fig. 8 numeral 170). It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the bottom select gate contacts in Lee with the bottom select gate portions in Sun in order to connect peripheral elements such as circuits, dies, etc. to the device and apply electrical signals to the bottom select gate (Lee, Par. [0029]).
For claim 6, Lee and Sun teach all of claim 1. Lee also teaches a staircase structure formed in the alternating conductor/dielectric layer stack (Lee, fig. 7G), wherein the alternating conductor/dielectric layer stack includes a plurality of conductive layers (fig. 7G numeral 130) and dielectric layers (fig. 7G numeral 140) arranged alternatively in the vertical direction.
For claim 7, Lee and Sun teach all of claim 6. Lee also teaches a plurality of memory strings vertically extending through the alternating conductor/dielectric layer stack (Lee, fig. 7G numeral 110; fig. 5 numeral 110), the plurality of memory strings each comprising: a core filling film in a center (fig. 7G numeral 115), a channel layer surrounding the core filling film (fig. 7G numeral 111), and a memory film surrounding the channel layer (fig. 7G numeral 113).
For claim 8, Lee and Sun teach all of claim 7. Lee also teaches a bottom select gate contact contacting the bottom select gate, wherein the bottom select gate contact is located at a side of the staircase structure away from the plurality of memory strings in the first direction (Lee, fig. 4 shows contacts 170 located away from the memory strings 110; fig. 8 numeral 170).
For claim 9, Lee teaches a three-dimensional memory device comprising: a first conductive layer (Lee, fig. 7G numeral 131); an alternating conductor/dielectric layer stack disposed over the first conductive layer in a vertical direction (fig. 7G numeral 130 and 140 shows alternating conductor and dielectric layers) wherein the alternating conductor/dielectric layer stack includes a plurality of second conductive layers and dielectric layers arranged alternatively in a vertical direction; a slit structure extending through the first conductive layer, the second conductive layers and the dielectric layers in the vertical direction (fig. 7G numeral 160); and wherein the slit structure extends along a first direction perpendicular to the vertical direction (fig. 8 numeral 162). Lee also teaches the bottom gate includes a first portion extending along the first direction and a second portion extending along a second direction perpendicular to the first direction (fig. 8 numeral GS). Lee is silent regarding an insulating structure extending through first conductive layer in the vertical direction and the insulating structure includes the second portion in contact with the slit structure.
Sun teaches a memory device including a slit structure (Sun, fig. 21 numeral 161-1 – 161-6) extending through the alternating conductor/dielectric layer stack (fig. 21 numeral 141 and 142e) and the first conductive layer (fig. 21 numeral 131-1, 132-1e) in a vertical direction and an insulating structure extending through the first conductive layer in the vertical direction (fig. 21 numeral 136-1). The insulating structure and the slit structure are shown to be in contact with each other in a second direction (fig. 21 and 22 direction Y) perpendicular to a first direction (fig. 21 direction X). Figure 22 also shows the insulating structure 136-1 and 136-2 in contact with slit structures 161-1 – 161-6.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the insulating structure in Sun with the slit structure in Lee in order to better isolate the first conductive layer portions by inserting dielectric material between portions of the first conductive layer.
For claim 10, Lee and Sun teach all of claim 9. Sun also teaches the first conductive layer includes a first segment and a second segment (Sun, fig. 22 numerals F-1 and F-2) disposed adjacent to the first segment in the second direction, wherein the insulating structure is disposed between the first segment and the second segment (fig. 22 numeral 136-1 and 136-2).
For claim 11, Lee and Sun teach all of claim 10. Sun also teaches the first segment that has a size in the second direction (Sun, fig. 22 numeral F-1) that is greater than a size of the second segment in the second direction (fig. 22 numeral F-2; direction Y matches the second direction in figure 21).
For claim 12, Lee and Sun teach all of claim 10. Sun also teaches the first segment (Sun, fig. 22 numeral F-1) comprising: a first portion extending along the first direction (fig. 22 direction X); and a second portion extending from the first portion in the second direction (fig. 22 direction Y).
For claim 13, Lee and Sun teach all of claim 12. Lee also teaches the first conductive layer including a first segment comprising a first and second portion (Lee, fig. 8 numeral GS shows the first bottom select gate segment comprising multiple portions), and wherein a contact structure contacts the first and second portions (fig. 8 numeral 170). It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the contact structure in Lee with the first conductive layer in Sun in order to connect peripheral elements such as circuits, dies, etc. to the device and apply electrical signals to the first conductive layer (Lee, Par. [0029]).
For claim 14, Lee and Sun teach all of claim 9. Lee also teaches a staircase structure formed in the alternating conductor/dielectric layer stack (Lee, fig. 7G), wherein the alternating conductor/dielectric layer stack includes a plurality of conductive layers (fig. 7G numeral 130) and dielectric layers (fig. 7G numeral 140) arranged alternatively in the vertical direction. Lee also teaches a plurality of memory strings vertically extending through the alternating conductor/dielectric layer stack (fig. 7G numeral 110; fig. 5 numeral 110), the plurality of memory strings each comprising: a core filling film in a center (fig. 7G numeral 115), a channel layer surrounding the core filling film (fig. 7G numeral 111), and a memory film surrounding the channel layer (fig. 7G numeral 113).
For claim 15, Lee and Sun teach all of claim 14. Lee also teaches a contact structure contacting the first conductive layer, wherein the contact structure is located at a side of the staircase structure away from the plurality of memory strings in the first direction (Lee, fig. 4 shows contacts 170 located away from the memory strings 110; fig. 8 numeral 170).
For claim 16, Lee teaches a method of forming a three-dimensional memory device comprising: forming a bottom select gate (Lee, fig. 7G numeral 131); forming an alternating conductor/dielectric layer stack disposed over the bottom select gate in a vertical direction (fig. 7G numeral 130 and 140 shows alternating conductor and dielectric layers); forming a slit structure extending through the alternating conductor/dielectric layer stack and the bottom select gate in the vertical direction (fig. 7G numeral 160); and wherein the slit structure extends along a first direction perpendicular to the vertical direction (fig. 8 numeral 162). Lee also teaches the bottom gate includes a first portion extending along the first direction and a second portion extending along a second direction perpendicular to the first direction (fig. 8 numeral GS). Lee is silent regarding forming a bottom select gate cut extending through the bottom select gate in the vertical direction and the bottom select gate cut structure includes the second portion in contact with the slit structure.
Sun teaches forming a memory device including forming a slit structure (Sun, fig. 21 numeral 161-1 – 161-6) extending through the alternating conductor/dielectric layer stack (fig. 21 numeral 141 and 142e) and the bottom select gate (fig. 21 numeral 131-1, 132-1e) in a vertical direction and forming a bottom select gate cut structure extending through the bottom select gate in the vertical direction (fig. 21 numeral 136-1). The bottom select gate cut structure and the slit structure are shown to be in contact with each other in a second direction (fig. 21 and 22 direction Y) perpendicular to a first direction (fig. 21 direction X). Figure 22 also shows the bottom select gate cut 136-1 and 136-2 in contact with slit structures 161-1 – 161-6.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine forming the bottom select gate cut structure in Sun with the slit structure in Lee in order to better isolate the bottom select gate portions by inserting dielectric material between portions of the bottom select gate.
For claim 17, Lee and Sun teach all of claim 16. Sun also teaches the bottom select gate includes a first bottom select gate segment and a second bottom select gate segment (Sun, fig. 22 numerals F-1 and F-2) disposed adjacent to the first bottom select gate segment in the second direction, wherein the bottom select gate cut structure is disposed between the first bottom select gate segment and the second bottom select gate segment (fig. 22 numeral 136-1 and 136-2).
For claim 18, Lee and Sun teach all of claim 17. Sun also teaches the first bottom select gate segment that has a size in the second direction (Sun, fig. 22 numeral F-1) that is greater than a size of the second bottom select gate segment in the second direction (fig. 22 numeral F-2; direction Y matches the second direction in figure 21).
For claim 19, Lee and Sun teach all of claim 17. Sun also teaches the first bottom select gate segment (Sun, fig. 22 numeral F-1) comprising: a first portion extending along the first direction (fig. 22 direction X); and a second portion extending from the first portion in the second direction (fig. 22 direction Y).
For claim 20, Lee and Sun teach all of claim 19. Lee also teaches forming a bottom select gate contact contacting the bottom select gate (Lee, fig. 8 numeral 170), wherein the bottom select gate contact is located at a side of a staircase structure (fig. 7G shows a staircase structure) away from a plurality of memory strings in the first direction (fig. 7G numeral 110; fig. 5 numeral 110; fig. 3 numeral 110).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB T NELSON whose telephone number is (571)272-1031. The examiner can normally be reached Monday through Friday 9:00 AM to 5:00 PM.
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/J.T.N./Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815
Prosecution Insights