DETAILED ACTION
This action is responsive to the application filed 9 Sep 2024 and the Information Disclosure Statements filed 9 Sep 2024 and 24 Jun 2025. Claims 1-19 are pending. Claims 1 and 11 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice of Foreign Priority Claim
Acknowledgment is made of applicant’s claim for foreign priority. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 9 Sep 2024 and 24 Jun 2025 are acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Application Title
The Examiner proposes the below Application Title change in accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the title. The Applicant can suggest an alternative title if desired. The Application Title should be changed to the following:
“MEMORY CELLS WITH DUAL WORD LINE AND DUAL BIT LINE DRIVERS IN A MEMORY DEVICE”
Allowable Subject Matter
Claims 5 – 7 and 15 – 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 3, 8 – 13, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, et al, U.S. Patent Application Publication 2016/0172026 (“Lee”) in view of Lin, et al, U.S. Patent Application Publication 2021/0134352 (“Lin”).
Regarding claim 1, Lee teaches:
A memory device comprising: a memory cell array that including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells respectively connected to one of the plurality of bit lines and one of the plurality of word lines, the memory cell array in which first to ninth areas are set; (Lee, fig 12, “[0151] The memory cell array 100 is connected to the row decoder 420 via a plurality of word lines WL1, WL2, … WLn. The memory cell array 100 is connected to sensing circuits 200-1 to 200-n of the sensing circuit unit 250 via a plurality of bit lines BL1 to BLn. The memory cell array 100 includes a plurality of memory blocks, each of which includes a plurality of memory cells for storing data.”; a typical memory array with plural memory cells connected to plural word lines and plural bit lines).
a first column switch circuit connected to the plurality of bit lines and provided on one end side in a first direction of the memory cell array; a second column switch circuit connected to the plurality of bit lines and provided on the other end side in the first direction of the memory cell array; (Lee, fig 10, “[0135] Referring to FIG. 10, if sensing circuits 200-1 and 200-2 are placed at the right on the drawing basis, a second column gate unit including column gates CG2, CG4, and CG6, a second local I/O line unit SI/O, and sensing lines SEL1 to SELn are added at the left side of the drawing. A first column gate unit including column gates CG1, CG3, and CGS and a first local I/O line unit FI/O are default components.”; a memory array with each memory cell attached to a bit line; each bit line attached to at least two switching elements, in fig 10 BL1 is connected to CG1 and CG2 switches).
wherein in a case where a memory cell in the first area is selected, the first and second column switch circuits and the first and second row switch circuits are activated, and in a case where a memory cell in the second area is selected, the first column switch circuit and the first row switch circuit are activated, and in a case where a memory cell in the third area is selected, the second column switch circuit and the first row switch circuit are activated, and in a case where a memory cell in the fourth area is selected, the second column switch circuit and the second row switch circuit are activated, and in a case where a memory cell in the fifth area is selected, the first column switch circuit and the second row switch circuit are activated, and in a case where a memory cell in the sixth area is selected, the first and second column switch circuits and the first row switch circuit are activated, and in a case where a memory cell in the seventh area is selected, the second column switch circuit and the first and second row switch circuits are activated, and in a case where a memory cell in the eighth area is selected, the first and second column switch circuits and the second row switch circuit are activated, and in a case where a memory cell in the ninth area is selected, the first column switch circuit and (Lee, fig 10, “[0136] For example, a first column selection line signal CSL1 is enabled when a memory cell connected to a first bit line is selected. [0137] As the first column gate CG1 is turned on by the first column selection line signal CSL1, a sensing current is supplied from a bit line to a selected memory cell. As the second column gate CG2 is turned on by the first column selection line signal CSL1, a sensing voltage is transferred via the first selecting line SEL1.”; that when a bit line is selected by the controller both bit line switches are activated. Note: “selecting” one of the switches in the claims does not prevent selection of a second switch. Deselecting a second switch (for either bit lines or word lines) has not been examined).
Lee does not explicitly teach:
a first row switch circuit connected to the plurality of word lines and provided on one end side in a second direction of the memory cell array; and a second row switch circuit connected to the plurality of word lines and provided on the other end side in the second direction of the memory cell array,
the first and second row switch circuits are activated..
Lin teaches:
a first row switch circuit connected to the plurality of word lines and provided on one end side in a second direction of the memory cell array; and a second row switch circuit connected to the plurality of word lines and provided on the other end side in the second direction of the memory cell array, (Lin, fig 5, “[0054] With reference to FIG. 4 and FIG. 5, the word line drivers 510 includes a front node WLN1 (i.e., a first node) of the word line WL and an end node WLN2 (i.e., a second node) of the word line WL, and a conducting CL is disposed between the front node WLN1 and the end node WLN2. [0050] By using the plurality of word line drivers connected to both sides of the word line and the conducting line, the word line may be charged from both a near side and a far side of the word line, thereby a RC delay is further reduced.”; a memory array with each memory cell attached to a word line; each word line is attached to at least two driving elements which are switches; that when one row is selected, both drivers are active).
the first and second row switch circuits are activated. (Lin, fig 5, “ [0050] By using the plurality of word line drivers connected to both sides of the word line and the conducting line, the word line may be charged from both a near side and a far side of the word line, thereby a RC delay is further reduced.”; that when a word line is activated, both word line drives at each end are activated).
In view of the teachings of Lin it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lin to Lee before the effective filing date of the claimed invention in order to teach memory array control. The teachings of Lin, in the same or in a similar field of endeavor with Lee, can combine Lin’s double control of a word line with Lee’s double control of a Bit Line. The two related control elements merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 2, Lee, as modified by Lin, teaches the memory device according to claim 1.
Lee further teaches wherein the memory cell array has a quadrangular layout, and the first area is disposed in a central region of the memory cell array, and the second area is disposed in a first corner region of the memory cell array, and the third area is disposed in a second corner region of the memory cell array, and the fourth area is disposed in a third corner region of the memory cell array, and the fifth area is disposed in a fourth corner region of the memory cell array, and the sixth area is disposed between the first, second, and third areas, and the seventh area is disposed between the first, third, and fourth areas, and the eighth area is disposed between the first, fourth, and fifth areas, and the ninth area is disposed between the first, second, and fifth areas. (Lee, fig 12, “[0151] The memory cell array 100 is connected to the row decoder 420 via a plurality of word lines WL1, WL2, … WLn. The memory cell array 100 is connected to sensing circuits 200-1 to 200-n of the sensing circuit unit 250 via a plurality of bit lines BL1 to BLn. The memory cell array 100 includes a plurality of memory blocks, each of which includes a plurality of memory cells for storing data.”; a typical memory array with plural memory cells connected to plural word lines and plural bit lines, here Lee teaches at least 3 bit lines and at least 3 word lines and the “division” is arbitrary because none of the switches in claim 1 have been “deactivated”).
Regarding claim 3, Lee, as modified by Lin, teaches the memory device according to claim 2.
Lee further teaches wherein the sixth area includes a first region, a second region, and a third region, and the seventh area includes a fourth region, a fifth region, and a sixth region, and the eighth area includes a seventh region, an eighth region, and a ninth region, and the ninth area includes a tenth region, an eleventh region, and a twelfth region, and the first region is provided between the first area, the second area, and the third area, and the second region is provided between the second area and the tenth region, and the third region is provided between the third area and the fourth region, and the fourth region is provided between the first area, the third area, and the fourth area, and the fifth region is provided between the third area and the first region, and the sixth region is provided between the fourth area and the seventh region, and the seventh region is provided between the first area, the fourth area, and the fifth area, and the eighth region is provided between the fourth area and the fourth region, and the ninth region is provided between the fifth area and the tenth region, and the tenth region is provided between the first area, the second area, and the fifth area, and the eleventh region is provided between the fifth area and the seventh region, and the twelfth region is provided between the second area and the first region. (Lee, fig 5, 12, “[0151] The memory cell array 100 is connected to the row decoder 420 via a plurality of word lines WL1, WL2, … WLn. The memory cell array 100 is connected to sensing circuits 200-1 to 200-n of the sensing circuit unit 250 via a plurality of bit lines BL1 to BLn. The memory cell array 100 includes a plurality of memory blocks, each of which includes a plurality of memory cells for storing data. [0105] The 2-by-2 memory cell array structure illustrated in FIG. 5 may be extended to an N-by-M memory cell array structure (N and M being a natural number of 3 or more).”; a typical memory array with plural memory cells connected to plural word lines and plural bit lines, here Lee teaches at least 3 bit lines and at least 3 word lines; that the number of arbitrary regions can be increased; the “divisions” are arbitrary because none of the switches in claim 1 have been “deactivated”).
Regarding claim 8, Lee, as modified by Lin, teaches the memory device according to claim 1.
Lee further teaches wherein one or both of the first and second column switch circuits are activated and one or both of the first and second row switch circuits are activated according to an address of a memory cell to be operated among the memory cells. (Lee, fig 10, “[0135] Referring to FIG. 10, if sensing circuits 200-1 and 200-2 are placed at the right on the drawing basis, a second column gate unit including column gates CG2, CG4, and CG6, a second local I/O line unit SI/O, and sensing lines SEL1 to SELn are added at the left side of the drawing. A first column gate unit including column gates CG1, CG3, and CGS and a first local I/O line unit FI/O are default components.”; a memory array with each memory cell attached to a bit line; each bit line attached to at least two switching elements, in fig 10 BL1 is connected to CG1 and CG2 switches, which are both activated by the same CSL signal).
Lin teaches one or both of the first and second row switch circuits are activated according to an address of a memory cell to be operated among the memory cells. (Lin, fig 5, “ [0050] By using the plurality of word line drivers connected to both sides of the word line and the conducting line, the word line may be charged from both a near side and a far side of the word line, thereby a RC delay is further reduced.”; a memory array with each memory cell attached to a word line; each word line is attached to at least two driving elements which are switches; that when one row is selected, both drivers are active).
In view of the teachings of Lin it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lin to Lee before the effective filing date of the claimed invention in order to teach memory array control. The teachings of Lin, in the same or in a similar field of endeavor with Lee, can combine Lin’s double control of a word line with Lee’s double control of a Bit Line. The two related control elements merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 9, Lee, as modified by Lin, teaches the memory device according to claim 1.
Lee further teaches wherein each of the memory cells includes a memory element, and a switching element connected in series to the memory element. (Lee, fig 13, “[0164] Referring to FIG. 13, the memory cell block contains a plurality of memory cells MC. Each memory cell MC includes a variable resistance element VR and a cell transistor CT. [0167] A gate of the cell transistor CT is connected to a word line WL. The cell transistor CT is switched on or off by a signal that is provided via the word line WL. A drain of the cell transistor CT is connected to the variable resistance element VR, and a source thereof is connected to a source line SL. [0166] The variable resistance element VR may be implemented using various elements. … or a Magnetic RAM (MRAM) using a ferromagnetic material.”; that the memory can have an ferromagnetic material; that the MC has two elements; a switching element powered by the WL, and a resistive element).
Regarding claim 10, Lee, as modified by Lin, teaches the memory device according to claim 9.
Lee further teaches wherein the memory element is a magnetoresistive effect element. (Lee, fig 13, “[0164] Referring to FIG. 13, the memory cell block contains a plurality of memory cells MC. Each memory cell MC includes a variable resistance element VR and a cell transistor CT. [0167] A gate of the cell transistor CT is connected to a word line WL. The cell transistor CT is switched on or off by a signal that is provided via the word line WL. A drain of the cell transistor CT is connected to the variable resistance element VR, and a source thereof is connected to a source line SL. [0166] The variable resistance element VR may be implemented using various elements. … or a Magnetic RAM (MRAM) using a ferromagnetic material.”; that the memory can have an ferromagnetic material; that the MC has two elements; a switching element powered by the WL, and a resistive element).
Regarding claim 11, Lee teaches:
A memory device comprising: a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells respectively connected to one of the plurality of bit lines and one of the plurality of word lines, the memory cell array in which first to ninth areas are set; (Lee, fig 12, “[0151] The memory cell array 100 is connected to the row decoder 420 via a plurality of word lines WL1, WL2, … WLn. The memory cell array 100 is connected to sensing circuits 200-1 to 200-n of the sensing circuit unit 250 via a plurality of bit lines BL1 to BLn. The memory cell array 100 includes a plurality of memory blocks, each of which includes a plurality of memory cells for storing data.”; a typical memory array with plural memory cells connected to plural word lines and plural bit lines).
a first column switch circuit connected to the plurality of bit lines and provided on one end side in a first direction of the memory cell array; a second column switch circuit connected to the plurality of bit lines and provided on the other end side in the first direction of the memory cell array; (Lee, fig 10, “[0135] Referring to FIG. 10, if sensing circuits 200-1 and 200-2 are placed at the right on the drawing basis, a second column gate unit including column gates CG2, CG4, and CG6, a second local I/O line unit SI/O, and sensing lines SEL1 to SELn are added at the left side of the drawing. A first column gate unit including column gates CG1, CG3, and CGS and a first local I/O line unit FI/O are default components.”; a memory array with each memory cell attached to a bit line; each bit line attached to at least two switching elements, in fig 10 BL1 is connected to CG1 and CG2 switches).
wherein one or both of the first and second column switch circuits are activated and (Lee, fig 10, “[0136] For example, a first column selection line signal CSL1 is enabled when a memory cell connected to a first bit line is selected. [0137] As the first column gate CG1 is turned on by the first column selection line signal CSL1, a sensing current is supplied from a bit line to a selected memory cell. As the second column gate CG2 is turned on by the first column selection line signal CSL1, a sensing voltage is transferred via the first selecting line SEL1.”; that when a bit line is selected by the controller both bit line switches are activated. Note: “selecting” one of the switches in the claims does not prevent selection of a second switch. Deselecting a second switch (for either bit lines or word lines) has not been examined).
Lee does not explicitly teach:
a first row switch circuit connected to the plurality of word lines and provided on one end side in a second direction of the memory cell array; and a second row switch circuit connected to the plurality of word lines and provided on the other end side in the second direction of the memory cell array,
one or both of the first and second row switch circuits are activated according to an address of a memory cell to be operated among the memory cells..
Lin teaches:
a first row switch circuit connected to the plurality of word lines and provided on one end side in a second direction of the memory cell array; and a second row switch circuit connected to the plurality of word lines and provided on the other end side in the second direction of the memory cell array, (Lin, fig 5, “[0054] With reference to FIG. 4 and FIG. 5, the word line drivers 510 includes a front node WLN1 (i.e., a first node) of the word line WL and an end node WLN2 (i.e., a second node) of the word line WL, and a conducting CL is disposed between the front node WLN1 and the end node WLN2. [0050] By using the plurality of word line drivers connected to both sides of the word line and the conducting line, the word line may be charged from both a near side and a far side of the word line, thereby a RC delay is further reduced.”; a memory array with each memory cell attached to a word line; each word line is attached to at least two driving elements which are switches; that when one row is selected, both drivers are active).
one or both of the first and second row switch circuits are activated according to an address of a memory cell to be operated among the memory cells. (Lin, fig 5, “ [0050] By using the plurality of word line drivers connected to both sides of the word line and the conducting line, the word line may be charged from both a near side and a far side of the word line, thereby a RC delay is further reduced.”; that when a word line is activated, both word line drives at each end are activated).
In view of the teachings of Lin it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lin to Lee before the effective filing date of the claimed invention in order to teach memory array control. The teachings of Lin, in the same or in a similar field of endeavor with Lee, can combine Lin’s double control of a word line with Lee’s double control of a Bit Line. The two related control elements merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 12, Lee, as modified by Lin, teaches the memory device according to claim 11.
Lee further teaches wherein the memory cell array has a quadrangular layout, and the first area is disposed in a central region of the memory cell array, and the second area is disposed in a first corner region of the memory cell array, and the third area is disposed in a second corner region of the memory cell array, and the fourth area is disposed in a third corner region of the memory cell array, and the fifth area is disposed in a fourth corner region of the memory cell array, and the sixth area is disposed between the first, second, and third areas, and the seventh area is disposed between the first, third, and fourth areas, and the eighth area is disposed between the first, fourth, and fifth areas, and the ninth area is disposed between the first, second, and fifth areas. (Lee, fig 12, “[0151] The memory cell array 100 is connected to the row decoder 420 via a plurality of word lines WL1, WL2, … WLn. The memory cell array 100 is connected to sensing circuits 200-1 to 200-n of the sensing circuit unit 250 via a plurality of bit lines BL1 to BLn. The memory cell array 100 includes a plurality of memory blocks, each of which includes a plurality of memory cells for storing data.”; a typical memory array with plural memory cells connected to plural word lines and plural bit lines, here Lee teaches at least 3 bit lines and at least 3 word lines and the “division” is arbitrary because none of the switches in claim 1 have been “deactivated”).
Regarding claim 13, Lee, as modified by Lin, teaches the memory device according to claim 12.
Lee further teaches wherein the sixth area includes a first region, a second region, and a third region, and the seventh area includes a fourth region, a fifth region, and a sixth region, and the eighth area includes a seventh region, an eighth region, and a ninth region, and the ninth area includes a tenth region, an eleventh region, and a twelfth region, and the first region is provided between the first area, the second area, and the third area, and the second region is provided between the second area and the tenth region, and the third region is provided between the third area and the fourth region, and the fourth region is provided between the first area, the third area, and the fourth area, and the fifth region is provided between the third area and the first region, and the sixth region is provided between the fourth area and the seventh region, and the seventh region is provided between the first area, the fourth area, and the fifth area, and the eighth region is provided between the fourth area and the fourth region, and the ninth region is provided between the fifth area and the tenth region, and the tenth region is provided between the first area, the second area, and the fifth area, and the eleventh region is provided between the fifth area and the seventh region, and the twelfth region is provided between the second area and the first region. (Lee, fig 5, 12, “[0151] The memory cell array 100 is connected to the row decoder 420 via a plurality of word lines WL1, WL2, … WLn. The memory cell array 100 is connected to sensing circuits 200-1 to 200-n of the sensing circuit unit 250 via a plurality of bit lines BL1 to BLn. The memory cell array 100 includes a plurality of memory blocks, each of which includes a plurality of memory cells for storing data. [0105] The 2-by-2 memory cell array structure illustrated in FIG. 5 may be extended to an N-by-M memory cell array structure (N and M being a natural number of 3 or more).”; a typical memory array with plural memory cells connected to plural word lines and plural bit lines, here Lee teaches at least 3 bit lines and at least 3 word lines; that the number of arbitrary regions can be increased; the “divisions” are arbitrary because none of the switches in claim 1 have been “deactivated”).
Regarding claim 18, Lee, as modified by Lin, teaches the memory device according to claim 11.
Lee further teaches wherein each of the memory cells includes a memory element, and a switching element connected in series to the memory element. (Lee, fig 13, “[0164] Referring to FIG. 13, the memory cell block contains a plurality of memory cells MC. Each memory cell MC includes a variable resistance element VR and a cell transistor CT. [0167] A gate of the cell transistor CT is connected to a word line WL. The cell transistor CT is switched on or off by a signal that is provided via the word line WL. A drain of the cell transistor CT is connected to the variable resistance element VR, and a source thereof is connected to a source line SL. [0166] The variable resistance element VR may be implemented using various elements. … or a Magnetic RAM (MRAM) using a ferromagnetic material.”; that the memory can have an ferromagnetic material; that the MC has two elements; a switching element powered by the WL, and a resistive element).
Regarding claim 19, Lee, as modified by Lin, teaches the memory device according to claim 18.
Lee further teaches wherein the memory element is a magnetoresistive effect element. (Lee, fig 13, “[0164] Referring to FIG. 13, the memory cell block contains a plurality of memory cells MC. Each memory cell MC includes a variable resistance element VR and a cell transistor CT. [0167] A gate of the cell transistor CT is connected to a word line WL. The cell transistor CT is switched on or off by a signal that is provided via the word line WL. A drain of the cell transistor CT is connected to the variable resistance element VR, and a source thereof is connected to a source line SL. [0166] The variable resistance element VR may be implemented using various elements. … or a Magnetic RAM (MRAM) using a ferromagnetic material.”; that the memory can have an ferromagnetic material; that the MC has two elements; a switching element powered by the WL, and a resistive element).
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, as modified by Lin, in view of Parkinson, et al, U.S. Patent 10,311,921 (“Parkinson”).
Regarding claim 4, Lee, as modified by Lin, teaches the memory device according to claim 1.
Lee, as modified by Lin, does not explicitly teach:
further comprising: a global bit line connected to the first and second column switch circuits; and
a global word line connected to the first and second row switch circuits..
Parkinson teaches:
further comprising: a global bit line connected to the first and second column switch circuits; and (Parkinson, fig 4, “(91) For at least some example configurations, the bit line read voltage generator 408 may be configured as a current supply that generates and supplies a global bit line current I.sub.GBL.”; that global bit lines are typically used to drive a memory block’s local bit lines).
a global word line connected to the first and second row switch circuits. (Parkinson, fig 4, “(83) The word line read voltage generator 406 is configured to generate a global selected word line voltage V.sub.GWL.sub._.sub.SEL at a global selected word line node GWL_SEL. Through generation and/or supply of the global word line current I.sub.GWL, the word line read voltage generator 406 may be configured to drive the global selected word line”; that global word lines are typically used to drive a memory block’s local word lines).
In view of the teachings of Parkinson it would have been obvious for a person of ordinary skill in the art to apply the teachings of Parkinson to Lee before the effective filing date of the claimed invention in order to teach memory array control. The teachings of Parkinson, in the same or in a similar field of endeavor with Lee, can combine Parkinson’s global control lines with Lee’s unspecified control of an array with multiple blocks. The two related control elements merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 14, Lee, as modified by Lin, teaches the memory device according to claim 11.
Lee, as modified by Lin, does not explicitly teach:
further comprising: a global bit line connected to the first and second column switch circuits; and
a global word line connected to the first and second row switch circuits..
Parkinson teaches:
further comprising: a global bit line connected to the first and second column switch circuits; and (Parkinson, fig 4, “(91) For at least some example configurations, the bit line read voltage generator 408 may be configured as a current supply that generates and supplies a global bit line current I.sub.GBL.”; that global bit lines are typically used to drive a memory block’s local bit lines).
a global word line connected to the first and second row switch circuits. (Parkinson, fig 4, “(83) The word line read voltage generator 406 is configured to generate a global selected word line voltage V.sub.GWL.sub._.sub.SEL at a global selected word line node GWL_SEL. Through generation and/or supply of the global word line current I.sub.GWL, the word line read voltage generator 406 may be configured to drive the global selected word line”; that global word lines are typically used to drive a memory block’s local word lines).
In view of the teachings of Parkinson it would have been obvious for a person of ordinary skill in the art to apply the teachings of Parkinson to Lee before the effective filing date of the claimed invention in order to teach memory array control. The teachings of Parkinson, in the same or in a similar field of endeavor with Lee, can combine Parkinson’s global control lines with Lee’s unspecified control of an array with multiple blocks. The two related control elements merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825