Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-15 are objected to because of the following informalities:
Claim 1:
lines 2-3: “the graphical control model include” must have been --the graphical control model including-- or --wherein the graphical control model includes--.
line 5: replace “block pairs” with --one or more block pairs--.
line 9: replace “in which” with --wherein--.
line 16: “the scope of computational accuracy” must have been --a scope of computational accuracy--.
line 21: “this operation” must have been --the operation--.
Claim 2:
lines 2-3: replace “it corresponds” with --the control program corresponds--.
Claim 3:
line 2-3: replace “it corresponds” with --the control program corresponds--.
Claim 4:
line 2: replace “it corresponds” with --the control program corresponds--.
Claim 8:
line 2: replace “they” with --the first and second blocks--.
line 11: replace “they” with --the first and second blocks--.
Claim 9:
line 2: delete “(12)”.
Claim 10:
line 2: replace “created” with --generated--.
line 3: “it corresponds” with --the intermediate representation corresponds--.
Claim 11:
line 6: Delete “(Aux4)”
Claim 13:
line 12: “the processing unit” must have been --the at least one processing unit--.
Claim 14:
line 1: “a processor to carry out” must have been --a processor configured to carry out--.
Claim 15:
line 1: “the program” must have been --a program--.
Claims 2-12 are objected to for being dependent on claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 4, 11, 12, and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3 line 4, “the second reparameterized block” lacks proper antecedent basis. Furthermore, the claims do not recite any block as being reparameterized. Therefore, it is unclear if “the second reparameterized block” is referencing the first block or referencing the second block. For examination purposes, the claim will be treated as --a second reparameterized block--.
Regarding claim 4 lines 4-5, It is unclear whether or not the block diagram cited in claim 4 lines 4-5 is referencing the “multiply modified block diagram” cited in claim 4 line 2 or referencing the “block diagram” cited in claim 1 line 3. For examination purposes; the claim will be treated as referencing the “multiply modified block diagram” cited in claim 4 line 2.
Regarding claim 11 line 4, “the second reparameterized block” lacks proper antecedent basis. Furthermore, the claims do not recite any block as being reparameterized. Therefore, it is unclear if “the second reparameterized block” is referencing the first block or referencing the second block. For examination purposes, the claim will be treated as --a second reparameterized block--.
Regarding claim 12 lines 4-5, it is unclear whether or not the “generation of an optimized intermediate representation” cited in claim 12 lines 4-5 is referencing the “generating an intermediate representation” cited in claim 9 line 4, or a new instance of generating an intermediate representation. For examination purposes, the claim will be treated as --generation of the optimized intermediate representation--.
Regarding claim 13 line 6, it is unclear where or not claim 13 is referencing the “target platform” cited in claim 1 line 1 or referencing the “target platform” cited in claim 13 line 1. For examination purposes. The claim will be treated as referencing the target platform of claim 13 line 1.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 15 is rejected under 35 U.S.C. 101 because the claim invention is claim is directed toward non-statutory subject matter.
Regarding claim 15, the claim is directed toward “A computer program product”. “A computer program product” is considered “software per se”, which does not fall under one of the statutory categories. Therefore, the claim is directed toward non-statutory subject matter.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 7-10, and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Moors et al. (US20180088911, Moors hereinafter) in view of Odinaka et al. (US11748537, Odinaka hereinafter).
Regarding claim 1, Moors discloses: A computer-implemented method for creating a control program for a target platform from a graphical control model of a development platform, the graphical control model includes a block diagram with a plurality of blocks (Moors, see paragraph [0071], “Once correctness of the model has been established and reference data has been stored, the blocks corresponding to the control program are converted to program code via the production code generator PCG... Settings applied during the code generation may comprise a conversion to lower-precision operations that are computationally more efficient, e.g. integer instructions for fixed-point calculations, so that the control program later can be executed in real-time on the microcontroller of an embedded system”), (Moors, see paragraph [0082], “The test environment comprises a host environment for executing the control program OBJ on the host computer and a target environment for executing the control program OBJ* on the embedded system...”), (Moors, see paragraph [0069], “The modelling environment MOD of the TCE can comprise a graphical user interface for modifying a block diagram BLD, which may comprise a plurality of blocks interconnected by signal paths... the block diagram describes the predetermined or intended behavior of a control program...”), the method comprising:
identifying, when creating the control program for the target platform from the graphical control model, block pairs (“group of adjacent blocks”) that include a first block and a second block (Moors, see paragraph [0086], “Identifying, in step S101, blocks in the block diagram which comprise a write operation to a special medium...”), (Moors, see paragraph [0089], “Tracing back, in step S104, the composite signal to a second block upstream of the selected block, the selected block and the second block forming a group of adjacent blocks.”); and
connecting the first block and the second block to one another via at least one signal link such that an output of the first block drives an input of the second block (Moors, see paragraph [0056], “Multiple blocks may be connected by signals for the exchange of data... It may be said that the further block is downstream of the initial block because they are connected by a signal path so that data flows from the initial block to the further block.”), (Moors, see paragraph [0063], “In a first step S1, the selected one or more blocks (or, if selected, the entire block diagram) and related input data are transformed to an intermediate representation such as one or more hierarchical graphs. These hierarchical graphs may in particular comprise a data flow graph, a control flow graph and/or a tree structure...”).
Moors does not appear to distinctly disclose:
the first block and the second block are designed in such a way that an input signal of the first block, within a scope of computational accuracy that is necessary for executing the control program, and for all values in a value range that is necessary for executing the control program, corresponds to an output signal of the second block; or
the first block and the second block are designed in such a way that an input signal of the first block, within the scope of computational accuracy that is necessary for executing the control program, and for all values in a value range that is necessary for executing the control program, corresponds to an intermediate result of the second block, and the second block is designed in such a way that for an operation of the second block that uses the intermediate result, an input signal of this operation is replaceable.
However, Odinaka discloses:
the first block and the second block (back-to-back inverters) are designed in such a way that an input signal of the first block, within a scope of computational accuracy that is necessary for executing the control program, and for all values in a value range that is necessary for executing the control program, corresponds to an output signal of the second block (Odinaka, see col 31 lines 27-31, “...By the property of inversion, the following two functions are equivalent. Configuration 2501 can be minimized to configuration 2502. As such, the back-to-back inverters cancel each other, leading to an inverter count decrease of 2...”);
It would have been obvious to one of ordinary skill in the art before the effecting filing
date of the claimed invention to have modified a system for automatic code generation as taught by Moors, to include an input signal of a first block corresponding to an output signal of a second block as taught by Odinaka, for the result of reducing code size, memory consumption, and execution time, while preserving the functional behavior of the control program.
Regarding claim 2, Moors discloses:
wherein when a block pair that is designed (Moors, see paragraph [0064], “...In each step, an initial set of hierarchical graphs or an intermediate language is converted to a modified set of hierarchical graphs or an intermediate language while applying one or more optimization rules...”), (Moors, see paragraph [0065], “In a third step S3, the optimized intermediate representations such as optimized hierarchical graphs are translated to code in a high-level or low-level programming language, for example, C code...”).
Moors does not appear to distinctly disclose:
However, Odinaka discloses:
wherein when a block pair that is designed according to i) is identified, (“back-to-back inverters cancel each other”) (Odinaka, see col 31 lines 21-31, “...at block 2306, the CAD tool simplifies each of the 4r new MIGs by cancelling back-to-back inverters as illustrated in FIG. 25... During inverter minimization it can happen that two inverters are between the connection of two M-gates. By the property of inversion, the following two functions are equivalent. Configuration 2501 can be minimized to configuration 2502. As such, the back-to-back inverters cancel each other, leading to an inverter count decrease of 2...”).
It would have been obvious to one of ordinary skill in the art before the effecting filing
date of the claimed invention to have modified a system for automatic code generation as taught by Moors, to include a branch prior to a first block driving a successor block via an input signal of the first block while bypassing the first and second blocks as taught by Odinaka, for the result of reducing instruction count, memory consumption, and execution time while preserving functional behavior.
Regarding claim 4, Moors discloses:
wherein the control program is created in such a way that it corresponds to a multiply modified block diagram (Moors, see paragraph [0064], “...This optimization may comprise a plurality of intermediate steps on further intermediate representations between block level and production code level. In each step, an initial set of hierarchical graphs or an intermediate language is converted to a modified set of hierarchical graphs or an intermediate language while applying one or more optimization rules...”).
Moors does not appear to distinctly disclose:
However, Odinaka discloses:
(“K-MIG/4r new MIGs”), one or more further identifications of a block pair that is designed according to i) (Odinaka, see col 31 lines 21-33, “...at block 2306, the CAD tool simplifies each of the 4r new MIGs by cancelling back-to-back inverters as illustrated in FIG. 25... During inverter minimization it can happen that two inverters are between the connection of two M-gates... To avoid explosion in computation, inverter propagation is performed after the synthesis of each K-MIG as opposed to after the synthesis of the full logic circuit...”).
It would have been obvious to one of ordinary skill in the art before the effecting filing
date of the claimed invention to have modified a system for automatic code generation as taught by Moors, to include the identification of block pairs and corresponding modification of a block diagram as taught by Odinaka, for the result of optimizing the operations of the generated control program.
Regarding claim 7, Moors does not appear to distinctly disclose:
wherein the first and second blocks of the block pair carry out inverse operations and/or opposite operations.
However, Odinaka discloses:
wherein the first and second blocks of the block pair carry out inverse operations (Odinaka, see col 27 lines 27-31, “...By the property of inversion, the following two functions are equivalent. Configuration 2501 can be minimized to configuration 2502. As such, the back-to-back inverters cancel each other, leading to an inverter count decrease of 2...”).
It would have been obvious to one of ordinary skill in the art before the effecting filing
date of the claimed invention to have modified a system for automatic code generation as taught by Moors, to include a first and second block carrying out inverse operations as taught by Odinaka, for the result of reliably and efficiently locating redundant block pairs.
Regarding claim 8, Moors does not appear to distinctly disclose:
wherein the first and second blocks of the block pair are designed in such a way that they carry out: additive inverse operations, logical inverse operations, bitwise inverse operations, inverse mathematical functions, multiplicative inverse operations, opposite data type conversions, and/or linkages thereof; and/or wherein the first and second blocks of the block pair are designed in such a way that they carry out linkages of operations which as a whole are inverse to one another.
However, Odinaka discloses:
wherein the first and second blocks of the block pair are designed in such a way that they carry out: (Odinaka, see col 27 lines 27-31, “...By the property of inversion, the following two functions are equivalent. Configuration 2501 can be minimized to configuration 2502. As such, the back-to-back inverters cancel each other, leading to an inverter count decrease of 2...”).
It would have been obvious to one of ordinary skill in the art before the effecting filing
date of the claimed invention to have modified a system for automatic code generation as taught by Moors, to include a first and second block carrying out logical inverse operations as taught by Odinaka, for the result of reliably and efficiently locating redundant block pairs.
Regarding claim 9, Moors discloses: wherein creating the control program for the target platform from the graphical control model (12) of the development platform comprises the steps:
generating an intermediate representation from the graphical control model (Moors, see paragraph [0063], “In a first step S1, the selected one or more blocks (or, if selected, the entire block diagram) and related input data are transformed to an intermediate representation such as one or more hierarchical graphs. These hierarchical graphs may in particular comprise a data flow graph, a control flow graph and/or a tree structure...”);
optimizing the generated intermediate representation (Moors, see paragraph [0064], “In a second step S2, the hierarchical graphs are optimized in order to reduce the number of variables required and/or the number of operations or instructions to be carried out...”); and
creating the control program for the target platform by translating the optimized intermediate representation (Moors, see paragraph [0065], “In a third step S3, the optimized intermediate representations such as optimized hierarchical graphs are translated to code in a high-level or low-level programming language, for example, C code...”), and
wherein, at least one of the steps and/or the step of generating the intermediate representation includes (Moors, see paragraph [0064]).
Moors does not appear to distinctly disclose:
However, Odinaka discloses:
identifying block pairs that are designed according to i) (inverters must be identified to be canceled) (Odinaka, see col 31 lines 21-23, “...at block 2306, the CAD tool simplifies each of the 4r new MIGs by cancelling back-to-back inverters as illustrated in FIG. 25...”).
It would have been obvious to one of ordinary skill in the art before the effecting filing
date of the claimed invention to have modified a system for automatic code generation as taught by Moors, to include identifying block pairs according to i) as taught by Odinaka, for the result of locating redundant block pairs within the intermediate representation.
Regarding claim 10, Moors discloses:
(Moors, see paragraph [0064], “...In each step, an initial set of hierarchical graphs or an intermediate language is converted to a modified set of hierarchical graphs or an intermediate language while applying one or more optimization rules...”).
Moors does not appear to distinctly disclose:
wherein when a block pair that is designed according to i) is identified,
However, Odinaka discloses:
wherein when a block pair that is designed according to i) is identified, (Odinaka, see col 31 lines 21-31, “...at block 2306, the CAD tool simplifies each of the 4r new MIGs by cancelling back-to-back inverters as illustrated in FIG. 25... During inverter minimization it can happen that two inverters are between the connection of two M-gates... By the property of inversion, the following two functions are equivalent. Configuration 2501 can be minimized to configuration 2502. As such, the back-to-back inverters cancel each other, leading to an inverter count decrease of 2...”).
It would have been obvious to one of ordinary skill in the art before the effecting filing
date of the claimed invention to have modified a system for automatic code generation as taught by Moors, to include a branch prior to a first block driving a successor block via an input signal of the first block while bypassing the first and second blocks as taught by Odinaka, for the result of reducing instruction count, memory consumption, and execution time while preserving functional behavior.
Regarding claim 12, Moors does not appear to distinctly disclose: wherein the optimizing of the generated intermediate representation includes
renewed identification of block pairs that are designed according to i) and/or ii) in the modified block diagram corresponding to the intermediate representation, and/or
includes generation of an optimized intermediate representation that corresponds to a multiply modified block diagram in which after a first modification of the block diagram, one or more further identifications of a block pair that is designed according to i) and/or ii) and corresponding modification of the block diagram take place.
However, Odinaka discloses: wherein the optimizing of the generated intermediate representation includes
renewed identification of block pairs that are designed according to i) (Odinaka, see col 31 lines 21-33, “...at block 2306, the CAD tool simplifies each of the 4r new MIGs by cancelling back-to-back inverters as illustrated in FIG. 25... During inverter minimization it can happen that two inverters are between the connection of two M-gates... To avoid explosion in computation, inverter propagation is performed after the synthesis of each K-MIG as opposed to after the synthesis of the full logic circuit...”).
It would have been obvious to one of ordinary skill in the art before the effecting filing
date of the claimed invention to have modified a system for automatic code generation as taught by Moors, to include the renewed identification of block pairs that are designed according to i) in the modified block diagram corresponding to the intermediate representation as taught by Odinaka, for the result of reducing instruction count, memory consumption, and execution time while preserving functional behavior.
Regarding claim 13, Moors discloses: A method for configuring a target platform designed as a control unit, the target platform comprising at least one processing unit and at least one sensor and/or actuator for detecting data of a physical process (Moors, see paragraph [0083], “When a processor-in-the-loop simulation is performed, the production code is cross-compiled on the host computer to create an executable OBJ* that is subsequently being run on another processor, in particular a microcontroller of an embedded system...”), (Moors, see paragraph [0051], “The embedded system ES comprises a network interface NC, an actuator interface AI and a sensor interface SI as well as a microcontroller MC...”), the method comprising:
reading in a graphical control model of a development platform (Moors, see paragraph [0063], “In a first step S1, the selected one or more blocks (or, if selected, the entire block diagram) and related input data are transformed to an intermediate representation such as one or more hierarchical graphs. These hierarchical graphs may in particular comprise a data flow graph, a control flow graph and/or a tree structure...”);
creating a control program for the target platform from the read-in graphical control model using the method according to claim 1 (Moors, see paragraph [0071], “Once correctness of the model has been established and reference data has been stored, the blocks corresponding to the control program are converted to program code via the production code generator PCG... Settings applied during the code generation may comprise a conversion to lower-precision operations that are computationally more efficient, e.g. integer instructions for fixed-point calculations, so that the control program later can be executed in real-time on the microcontroller of an embedded system”), (Moors, see paragraph [0082], “The test environment comprises a host environment for executing the control program OBJ on the host computer and a target environment for executing the control program OBJ* on the embedded system...”);
generating an executable code for the processing unit of the target platform by compiling the created control program; transferring the generated executable code to the target platform (Moors, see paragraph [0071], “...The generated production code is then compiled to object code or an executable using the production code compiler PCO; an object code is binary data that contains instructions for a particular processor...”), (Moors, see paragraph [0083]) and/or
executing the generated executable code by the processing unit of the target platform (Moors, see paragraph [0083]), (Moors, see paragraph [0051], “...The embedded system may comprise a non-volatile memory that comprises instructions to be carried out by the microcontroller or a configuration to be loaded on the programmable logic device.”).
Regarding claim 14, Moors discloses: A device for data processing, comprising a processor to carry out the method according to claim 1 (Moors, see paragraph [0050], “The host computer PC comprises at least one processor CPU with one or multiple cores, a random access memory RAM and a number of devices connected to a local bus (such as PCI Express), which exchanges data with the CPU via a bus controller BC...”).
Regarding claim 15, Moors discloses: A computer program product that includes commands which, when the program is executed by a computer, prompt the computer to carry out the method according to claim 1 (Moors, see paragraph [0050], “the non-volatile memory comprises instructions that, when executed by one or more cores of the processor CPU, cause the computer system to carry out a method according to one of the claims.”).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Moors and Odinaka as applied to claim 1 above, and further in view of Scherle et al. (US20210034337, Scherle hereinafter).
Regarding claim 5, Moors as modified does not appear to distinctly disclose:
wherein when a block pair that is designed according to i) and/or ii) is identified during creation of the control program, a warning is generated.
However, Scherle discloses:
wherein when a block pair that is designed according to i) (Scherle, paragraph [0042], “…A rule may comprise a filter that matches once a predetermined condition is fulfilled and an action to be performed in case of a match. The action may comprise outputting a warning and/or adjusting one or more code generation parameters, in particular scaling parameters.”), (Scherle, paragraph [0064], “In step S57… the processor verifies if the filter condition associated with the current rule is fulfilled, i.e. if the filter of the rule matches. When this is the case, in step S58 (Info/Change) a message is output to the user; alternatively or additionally, a graphical user interface for changing a scaling parameter or confirming a proposed change of the scaling parameter may be shown to the user…”), (Scherle, see paragraph [0075], “For block sum_yu, a rule may be processed: If the least significant bit of block sum_yu is less than the least significant bit of output port y, the processor outputs a warning message to the user…”), (Scherle, see paragraph [0065], “Once all rules have been applied, comprising interactive review of the messages and/or performing changes to relevant parameters, the block diagram is processed further in step S59 (Further Processing). This may comprise adapting other parts of the model/block diagram; when the whole model is adapted, production code may be generated for the block diagram.”).
It would have been obvious to one of ordinary skill in the art before the effecting filing
date of the claimed invention to have modified a system for automatic code generation as taught by Moors, to include the generation of a warning as taught by Scherle, for the result of facilitating the correction of the underlying modeling flaw.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Moors and Odinaka as applied to claim 1 above, and further in view of Szpak et al. (US20070282586, Szpak hereinafter).
Regarding claim 6, Moors as modified does not appear to distinctly disclose:
wherein the second block of the block pair is designed as a selector block or as an assignment block.
However, Szpak discloses:
wherein the second block (“bus selector block 208”) of the block pair is designed as a selector block (Szpak, see paragraph [0050], “…the bus creator block 206 is used to bundle together a plurality of component signals in the block diagram to form a single bus signal 210. The single bus signal 210 then connects the two sections of the model 200. At the destination end of the bus signal 210, a bus selector block 208 helps un-bundle the component signals 22, 24 and 26 so that each individual component signal 22, 24 or 26 can be connected to other blocks…”), (Szpak, see paragraph [0051], “…The bus selector block, which ungroups a bus signal, accepts input from a bus creator block or another bus selector block. The bus selector has one input and multiple output ports, depending on the number of signals to be de-grouped.”).
It would have been obvious to one of ordinary skill in the art before the effecting filing
date of the claimed invention to have modified a system for automatic code generation as taught by Moors, to include the designation of a selector block as taught by Szpak, for the result of reducing instruction count, memory consumption, and execution time while preserving functional behavior.
Allowable Subject Matter
Claims 3 and 11 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to remove condition i), leaving only condition ii) with the corrected forms of claims 3 and 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to Joshua Tran whose telephone number is (571)272-5460.
The examiner can normally be reached on M-F 9-5.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
supervisor, Hyung Sough can be reached on (571)272-6799. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSHUA TRAN/
Examiner, Art Unit 2192
/S. Sough/SPE, Art Unit 2192
Prosecution Insights