DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-18 are pending, of which all pending claims are rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Parthasarathy et al. (US 2017/0163287 A1), (hereinafter Parthasarathy).
Regarding claim 1, Parthasarathy teaches, a memory system (Parthasarathy: ‘memory 210’ [Fig.2] & [0033]) comprising: a non-volatile memory (Parthasarathy: ‘NAND flash memory device’ [Fig.2, block 210] & [0033]) configured to store a concatenated code (Parthasarathy: ‘concatenated code,’ “[0022] ….. In such an example case, all four inner LDPC codewords could be corrected by such a concatenated coding scheme.”) of a first error-correcting code generated using data to be stored (Parthasarathy: ‘the inner decoder and the outer decoder decodes the data using first and second error correcting codes respectively’ [0016]) and a second error-correcting code generated using the first error-correcting code (Parthasarathy: ‘only the decoding process/steps are explained, but the decoding process is the reverse of an encoding process’ “[0004] ..... Decoders configured to decode data encoded with such codes (hereinafter referred to as a “codeword”)”); and a memory controller (Parthasarathy: ‘controller 200’ [Fig.2] & [0033]) configured to: read, from the non-volatile memory, read information (Parthasarathy: ‘controller 200 reads first and second codewords from memory 210’ [Fig.2, blocks 200, 210 & 220] & [Fig.1, blocks 110-120] & [0025]); execute a second decoding processing using the second error-correcting code on the read information (Parthasarathy: ‘decoding a first codeword and a second codeword using an inner decoder’, “[0025-0027] Decoding the first and second codewords using a first decoder in the operational blocks 130 and 140 of certain embodiments can include using an inner decoder to decode inner codewords consisting of the hard data read in the operational blocks 110 and 120 using a first ECC decoding procedure.”); execute a first decoding processing using the first error-correcting code on the read information when decoding by the second decoding processing fails (Parthasarathy: ‘decoding a third codeword using an outer decoder’, “[0029] Decoding a third codeword using a second decoder to provide decoded data in the operational block 150 of certain embodiments can include using an outer decoder to decode the third codeword formed by the first and second results provided in the operational blocks 130 and 140.”); when the first decoding processing or a checking processing of checking that the read information does not include an error by using the first error-correcting code succeeds, generate a first parity bit that is a parity bit of the second error-correcting code, and calculate a first evaluation value for determining whether or not the read information includes the error by using the generated first parity bit and a second parity bit that is a parity bit of the second error-correcting code after the second decoding processing is executed (Parthasarathy: ‘detect and correct residual errors’ “[0013, 0016] … In certain embodiments described herein, the resources (e.g., ECC bits) of a first code (e.g., BCH code) are pooled for multiple inner codewords (e.g., LDPC codewords), such as to more efficiently utilize the redundancy of the first code by offering the pooled first code resources to codewords of a second code (e.g., LDPC code) that may be in need of extra correction. For example, in at least some of the disclosed embodiments, an inner decoder (e.g., a LDPC decoder) can run up to a particular number of iterations (e.g., a single iteration) to do as much error correction as possible with the limited number of iterations. An outer decoder (e.g., a BCH decoder) can be used to correct residual errors left after the inner decoder (e.g., the LDPC decoder) runs its limited number of iterations. The outer decoder can also deal with potential error floor or miscorrection issues arising from the use of the inner code decoder…”; ‘the decoded data are evaluated using error detection codes to check if there are any errors’ “[0030] An evaluation of whether the decoded data includes an error in the operational block 160 of certain embodiments can comprise generating a signal indicative of whether the decoded data includes at least one bit error or whether the decoded data does not include at least one bit error. In certain embodiments, the evaluation can be performed by the outer decoder (e.g., BCH decoder), while in certain other embodiments, the evaluation can be performed by an evaluation module separate from the outer decoder, with the evaluation module utilizing error detection codes (EDCs) such as cyclic redundancy check (CRC) codes.”); and determine whether or not the read information includes the error by using the first evaluation value (Parthasarathy: ‘the decoded data are evaluated using error detection codes to check if there are any errors’ “[0030] An evaluation of whether the decoded data includes an error in the operational block 160 of certain embodiments can comprise generating a signal indicative of whether the decoded data includes at least one bit error or whether the decoded data does not include at least one bit error. In certain embodiments, the evaluation can be performed by the outer decoder (e.g., BCH decoder), while in certain other embodiments, the evaluation can be performed by an evaluation module separate from the outer decoder, with the evaluation module utilizing error detection codes (EDCs) such as cyclic redundancy check (CRC) codes.”).
Regarding claim 10, Parthasarathy teaches, a method of controlling a non-volatile memory (Parthasarathy: ‘NAND flash memory device’ [Fig.2, block 210] & [0033]) configured to store a concatenated code (Parthasarathy: ‘concatenated code,’ “[0022] ….. In such an example case, all four inner LDPC codewords could be corrected by such a concatenated coding scheme.”) of a first error-correcting code generated using data to be stored (Parthasarathy: ‘the inner decoder and the outer decoder decodes the data using first and second error correcting codes respectively’ [0016]) and a second error-correcting code generated using the first error-correcting code (Parthasarathy: ‘only the decoding process/steps are explained, but the decoding process is the reverse of an encoding process’ “[0004] ..... Decoders configured to decode data encoded with such codes (hereinafter referred to as a “codeword”)”), the method comprising: reading, from the non-volatile memory, read information (Parthasarathy: ‘controller 200 reads first and second codewords from memory 210’ [Fig.2, blocks 200, 210 & 220] & [Fig.1, blocks 110-120] & [0025]); executing a second decoding processing using the second error-correcting code on the read information (Parthasarathy: ‘decoding a first codeword and a second codeword using an inner decoder’, “[0025-0027] Decoding the first and second codewords using a first decoder in the operational blocks 130 and 140 of certain embodiments can include using an inner decoder to decode inner codewords consisting of the hard data read in the operational blocks 110 and 120 using a first ECC decoding procedure.”); executing a first decoding processing using the first error-correcting code on the read information when decoding by the second decoding processing fails (Parthasarathy: ‘decoding a third codeword using an outer decoder’, “[0029] Decoding a third codeword using a second decoder to provide decoded data in the operational block 150 of certain embodiments can include using an outer decoder to decode the third codeword formed by the first and second results provided in the operational blocks 130 and 140.”); when the first decoding processing or a checking processing of checking that the read information does not include an error by using the first error-correcting code succeeds, generating a first parity bit that is a parity bit of the second error-correcting code, and calculating a first evaluation value for determining whether or not the read information includes the error by using the generated first parity bit and a second parity bit that is a parity bit of the second error-correcting code after the second decoding processing is executed (Parthasarathy: ‘detect and correct residual errors’ “[0013, 0016] … In certain embodiments described herein, the resources (e.g., ECC bits) of a first code (e.g., BCH code) are pooled for multiple inner codewords (e.g., LDPC codewords), such as to more efficiently utilize the redundancy of the first code by offering the pooled first code resources to codewords of a second code (e.g., LDPC code) that may be in need of extra correction. For example, in at least some of the disclosed embodiments, an inner decoder (e.g., a LDPC decoder) can run up to a particular number of iterations (e.g., a single iteration) to do as much error correction as possible with the limited number of iterations. An outer decoder (e.g., a BCH decoder) can be used to correct residual errors left after the inner decoder (e.g., the LDPC decoder) runs its limited number of iterations. The outer decoder can also deal with potential error floor or miscorrection issues arising from the use of the inner code decoder…”; ‘the decoded data are evaluated using error detection codes to check if there are any errors’ “[0030] An evaluation of whether the decoded data includes an error in the operational block 160 of certain embodiments can comprise generating a signal indicative of whether the decoded data includes at least one bit error or whether the decoded data does not include at least one bit error. In certain embodiments, the evaluation can be performed by the outer decoder (e.g., BCH decoder), while in certain other embodiments, the evaluation can be performed by an evaluation module separate from the outer decoder, with the evaluation module utilizing error detection codes (EDCs) such as cyclic redundancy check (CRC) codes.”); and determining whether or not the read information includes the error by using the first evaluation value (Parthasarathy: ‘the decoded data are evaluated using error detection codes to check if there are any errors’ “[0030] An evaluation of whether the decoded data includes an error in the operational block 160 of certain embodiments can comprise generating a signal indicative of whether the decoded data includes at least one bit error or whether the decoded data does not include at least one bit error. In certain embodiments, the evaluation can be performed by the outer decoder (e.g., BCH decoder), while in certain other embodiments, the evaluation can be performed by an evaluation module separate from the outer decoder, with the evaluation module utilizing error detection codes (EDCs) such as cyclic redundancy check (CRC) codes.”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 7-9, 11 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Parthasarathy et al. (US 2017/0163287 A1) in view of Watanabe et al. (US 2017/0187395 A1), (hereinafter Parthasarathy-Watanabe).
Regarding claim 2, Parthasarathy does not explicitly disclose, the memory system according to claim 1, wherein the second error-correcting code includes an N-dimensional error-correcting code in which at least one symbol of symbols forming a code is protected by N component code groups, N being an integer of 2 or more, the second decoding processing includes decoding M (1 ≤ i ≤ N, where ni is a number of component codes included in the i-th dimensional component code group, and M is a sum of ni) component codes included in the read information, and the memory controller is configured to: generate first parity bits for the M component codes when the checking processing determines that no error is included in the read information; and calculate the first evaluation value by using the generated M first parity bits and second parity bits of the M component codes after the second decoding processing is executed.
However, Watanabe et al. teaches in an analogous art, ‘two-dimensional error correcting component code that protects data in the column direction and in the row direction’ “[0202] In the respective embodiments described above, the product code that doubly protects the user data by two-dimensional component codes of the component codes in the column direction and the component codes in the row direction has been illustrated. … a code that protects at least a part of the user data more than doubly by the component codes in the form of two-dimensional or more can be used. In the description below, codes that protect the user data at least a part of doubly or more by the component codes in the form of two-dimensional or more…”
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Parthasarathy’s teachings of ‘concatenated coding scheme using inner and outer codewords’ with Watanabe’s teaching of ‘multi-dimensional error correction code’ to provide a memory controller for controlling a nonvolatile memory in which multi-dimensional error correction code having two or more component codes is stored, the memory controller perform a first decoding process and a second decoding process to determine whether the first rewriting process is erroneous correction based on a result of the second decoding process. By doing so, an erroneously corrected component code and a component code failed in calculation are rolled back (returned) to a component code in a state before erroneous correction and failed calculation are performed, to continue the decoding process thereafter. Therefore, the probability of decoding success can be further increased.
Regarding claim 7, Parthasarathy-Watanabe teaches, the memory system according to claim 1, wherein the second error-correcting code includes an N-dimensional error-correcting code in which at least one symbol of symbols forming a code is protected by N component code groups, N being an integer of 2 or more, the second decoding processing includes decoding M (1 ≤ i ≤ N, where ni is a number of component codes included in the i-th dimensional component code group, and M is a sum of ni) component codes included in the read information, and the memory controller is configured to execute the checking processing by using the first error-correcting code and a second evaluation value based on reliabilities of correction of the M component codes by the second decoding processing, each of the reliabilities of correction corresponding to each of the M component codes (Watanabe: ‘multi-dimensional error correction code having two or more component codes’ “[0033] According to an embodiment, a memory controller that controls a nonvolatile memory in which multi-dimensional error correction code having two or more component codes is stored, the memory controller comprising: a memory interface that reads out the multi-dimensional error correction code; a receiving unit configured to acquire a received word of the multi-dimensional error correction code; an intermediate decoded word memory that holds an intermediate decoded word of the multi-dimensional error correction code; a decoder configured to perform a decoding process and detect information relating to an error symbol;…”).
Regarding claim 8, Parthasarathy-Watanabe teaches, the memory system according to claim 7, wherein the second evaluation value includes: a number of component codes in which a syndrome is satisfied and the reliability is equal to or greater than a second threshold value, among the M component codes; a number of component codes of which the reliability is equal to or greater than the second threshold value, among the M component codes; or a sum of the reliabilities (Watanabe: ‘the reliability of component code’ [0198]).
Regarding claim 9, Parthasarathy-Watanabe teaches, the memory system according to claim 1, wherein the second error-correcting code includes an N-dimensional error-correcting code in which at least one symbol of symbols forming a code is protected by N component code groups, N being an integer of 2 or more, the second decoding processing includes decoding M (1 ≤ i ≤ N, where ni is a number of component codes included in the i-th dimensional component code group, and M is a sum of ni) component codes included in the read information, and the memory controller is configured to execute the checking processing every time each of the M component codes is decoded (Watanabe: ‘multi-dimensional error correction code having two or more component codes’ “[0033] According to an embodiment, a memory controller that controls a nonvolatile memory in which multi-dimensional error correction code having two or more component codes is stored, the memory controller comprising: a memory interface that reads out the multi-dimensional error correction code; a receiving unit configured to acquire a received word of the multi-dimensional error correction code; an intermediate decoded word memory that holds an intermediate decoded word of the multi-dimensional error correction code; a decoder configured to perform a decoding process and detect information relating to an error symbol;…”).
Regarding claim 11, Parthasarathy-Watanabe teaches, the method according to claim 10, wherein the second error-correcting code includes an N-dimensional error-correcting code in which at least one symbol of symbols forming a code is protected by N component code groups, N being an integer of 2 or more, the second decoding processing includes decoding M (1 ≤ i ≤ N, where ni is a number of component codes included in the i-th dimensional component code group, and M is a sum of ni) component codes included in the read information, and the method comprises: generating first parity bits for the M component codes when the checking processing determines that no error is included in the read information; and calculating the first evaluation value by using the generated M first parity bits and second parity bits of the M component codes after the second decoding processing is executed (Watanabe: ‘two-dimensional error correcting component code that protects data in the column direction and in the row direction’ [0202]).
Regarding claim 16, Parthasarathy-Watanabe teaches, the method according to claim 10, wherein the second error-correcting code includes an N-dimensional error-correcting code in which at least one symbol of symbols forming a code is protected by N component code groups, N being an integer of 2 or more, the second decoding processing includes decoding M (1 ≤ i ≤ N, where ni is a number of component codes included in the i-th dimensional component code group, and M is a sum of ni) component codes included in the read information, and the method comprises executing the checking processing by using the first error-correcting code and a second evaluation value based on reliabilities of correction of the M component codes by the second decoding processing, each of the reliabilities of correction corresponding to each of the M component codes (Watanabe: ‘multi-dimensional error correction code having two or more component codes’ “[0033] According to an embodiment, a memory controller that controls a nonvolatile memory in which multi-dimensional error correction code having two or more component codes is stored, the memory controller comprising: a memory interface that reads out the multi-dimensional error correction code; a receiving unit configured to acquire a received word of the multi-dimensional error correction code; an intermediate decoded word memory that holds an intermediate decoded word of the multi-dimensional error correction code; a decoder configured to perform a decoding process and detect information relating to an error symbol;…”).
Regarding claim 17, Parthasarathy-Watanabe teaches, the method according to claim 16, wherein the second evaluation value includes: a number of component codes in which a syndrome is satisfied and the reliability is equal to or greater than a second threshold value, among the M component codes; a number of component codes of which the reliability is equal to or greater than a second threshold value, among the M component codes; or a sum of the reliabilities (Watanabe: ‘the reliability of component code’ [0198]).
Regarding claim 18, Parthasarathy-Watanabe teaches, the method according to claim 10, wherein the second error-correcting code includes an N-dimensional error-correcting code in which at least one symbol of symbols forming a code is protected by N component code groups, N being an integer of 2 or more, the second decoding processing includes decoding M (1 ≤ i ≤ N, where ni is a number of component codes included in the i-th dimensional component code group, and M is a sum of ni) component codes included in the read information, and the method comprises executing the checking processing every time each of the M component codes is decoded (Watanabe: ‘multi-dimensional error correction code having two or more component codes’ “[0033] According to an embodiment, a memory controller that controls a nonvolatile memory in which multi-dimensional error correction code having two or more component codes is stored, the memory controller comprising: a memory interface that reads out the multi-dimensional error correction code; a receiving unit configured to acquire a received word of the multi-dimensional error correction code; an intermediate decoded word memory that holds an intermediate decoded word of the multi-dimensional error correction code; a decoder configured to perform a decoding process and detect information relating to an error symbol;…”).
Claims 3-6 and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Parthasarathy et al. (US 2017/0163287 A1) in view of Watanabe et al. (US 2017/0187395 A1), and further in view of Kravitz et al. (US 2008/0155372 A1), (hereinafter Parthasarathy-Watanabe-Kravitz).
Regarding claim 3, Parthasarathy-Watanabe does not explicitly disclose, the memory system according to claim 2, wherein the memory controller is configured to calculate Hamming distances between the first parity bits and the second parity bits for the M component codes, and calculate the first evaluation value that is a number of component codes, among the M component codes, in which the Hamming distance is equal to or greater than a first threshold.
However, Kravitz et al. teaches in an analogous art, ‘Hamming distance (or Hamming Weight) value is calculated and compared with a threshold value to evaluate/determine and generate an error indication based on the comparison’ “[0054] … generating the error indicator includes determining a Hamming weight of the generated portion of the checksum bit vector and comparing the Hamming weight to a threshold. In an embodiment, the LDPC-encoded codeword is declared error-free if the Hamming weight is lower than the threshold. [0065] In an embodiment, error indication is made based on the Hamming distance between vectors z and q. This includes determining a count of the number of bits that differ between vectors z and q and using a pre-defined threshold to make error indication decisions. For example, if the calculated Hamming distance between vectors z and q is less than the pre-defined threshold, the frame is declared to be correctly decoded. Otherwise, the decoded frame is decided to have been in error.” (See also [0057, 0066, 0077, 0084]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Parthasarathy-Watanabe’s teachings of ‘concatenated coding scheme using inner and outer codewords, and multi-dimensional error correction code’ with Kravitz’s teaching of ‘error evaluation of a codeword using Hamming distance/weight’ to provide methods and apparatus for improving error indication performance. As doing so, once the Hamming weight of each of the component vectors is calculated, the Hamming weight of a vector can be determined and compared against the pre-determined threshold to make error indication decisions.
Regarding claim 4, Parthasarathy-Watanabe-Kravitz teaches, the memory system according to claim 2, wherein the memory controller is configured to calculate Hamming distances between the first parity bits and the second parity bits for the M component codes, and calculate the first evaluation value that is a sum of a predetermined number of Hamming distances, among the calculated M Hamming distances, in descending order (Kravitz: ‘Hamming distance (or Hamming Weight) value is calculated and compared with a threshold value for error evaluation’ [0054,0057,0065-0066,0077,0084]).
Regarding claim 5, Parthasarathy-Watanabe-Kravitz teaches, the memory system according to claim 2, wherein the memory controller is configured to calculate Hamming distances between the first parity bits and the second parity bits for one or more component codes to be corrected by the first decoding processing among the M component codes, and calculate the first evaluation value that is a statistical value of the calculated Hamming distances (Kravitz: ‘summed statistical value’ [0054, 0077]).
Regarding claim 6, Parthasarathy-Watanabe-Kravitz teaches, the memory system according to claim 5, wherein the statistical value of the calculated Hamming distances is a sum or an average value of the calculated Hamming distances (Kravitz: ‘summed value’ [0054, 0077]).
Regarding claim 12, Parthasarathy-Watanabe-Kravitz teaches, the method according to claim 11, further comprising: calculating Hamming distances between the first parity bits and the second parity bits for the M component codes, and calculating the first evaluation value that is a number of component codes, among the M component codes, in which the Hamming distance is equal to or greater than a first threshold (Kravitz: ‘Hamming distance (or Hamming Weight) value is calculated and compared with a threshold value to evaluate/determine and generate an error indication based on the comparison’ [0054,0057,0065,0066,0077,0084]).
Regarding claim 13, Parthasarathy-Watanabe-Kravitz teaches, the method according to claim 11, further comprising: calculating Hamming distances between the first parity bits and the second parity bits for the M component codes, and calculating the first evaluation value that is a sum of a predetermined number of Hamming distances, among the calculated M Hamming distances, in descending order (Kravitz: ‘Hamming distance (or Hamming Weight) value is calculated and compared with a threshold value for error evaluation’ [0054,0057,0065-0066,0077,0084]).
Regarding claim 14, Parthasarathy-Watanabe-Kravitz teaches, the method according to claim 11, further comprising: calculating Hamming distances between the first parity bits and the second parity bits for one or more component codes to be corrected by the first decoding processing among the M component codes, and calculating the first evaluation value that is a statistical value of the calculated M Hamming distances (Kravitz: ‘summed statistical value’ [0054, 0077]).
Regarding claim 15, Parthasarathy-Watanabe-Kravitz teaches, the method according to claim 14, wherein the statistical value of the calculated Hamming distances is a sum or an average value of the calculated Hamming distances (Kravitz: ‘summed value’ [0054, 0077]).
Citation of Pertinent Prior Art
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Conclusion
The following prior arts made of record, listed on form PTO-892, and not relied upon, if any, are considered pertinent to applicant's disclosure:
Alrod et al. (US 2013/0166986 A1) teaches “[0038] ….To illustrate, the second ECC encoder 112 may receive the data d.sub.1, d.sub.2, . . . d.sub.8 and may generate an estimation P.sub.JE of the joint parity. Comparing P.sub.JE with the stored P.sub.J can give an indication of undetected errors in the decoding process. According to an embodiment, if P.sub.JE and P.sub.J are not identical, the decoding will be considered a failure. According to another embodiment, if the Hamming distance between P.sub.JE and P.sub.J is less than (or equal to) a threshold T, the decoding will be considered as successful, while if the Hamming distance is larger than the threshold, the decoding will be declared as failure. The threshold T may be predefined or may be dynamically defined according to an expected number of errors in P.sub.J.”
When amending the claims, Applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
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/ENAMUL M KABIR/
Examiner, Art Unit 2112
/Shelly A Chase/Primary Examiner, Art Unit 2112