DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 9, 10, 12, 13, 15 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. US 2023/0038603 A1.
Regarding claims 1-7, 9, 10 and 12, Choi discloses:
A semiconductor package (Figs. 6A/6B) comprising:
a buffer die (100);
memory dies (para 0062; 200A, 200B1, 200B2, 200C) sequentially stacked on the buffer die;
a bonding layer (251b) that extends between ones of the memory dies, wherein the bonding layer is configured to bond ones of the memory dies with each other; and
a molding member (260) on the buffer die, wherein the molding member is on sidewalls of the memory dies,
wherein each of the memory dies includes:
a substrate (210) having first (bottom) and second (top) surfaces opposite to each other in a vertical direction substantially perpendicular to an upper surface of the buffer die; and
a first signal pad (see annotated Fig. 6B below; IOS portion “C”) and a test pad structure (ETS) on the first surface of the substrate,
wherein the test pad structure includes a test pad (see annotated Fig. 6B below; “A”) and a first conductive pattern (see annotated Fig. 6B below; “B”) stacked in the vertical direction on the first surface of the substrate, and
wherein the first conductive pattern has an uneven surface facing the substrate (“B” as a whole is shown with an uneven surface facing 210).
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(claim 2) annotated Fig. 6B above; “A” (inclusive of vias) shown with an uneven surface facing 210.
(claim 3) annotated Fig. 6B above; surface of “A” (inclusive of vias) shown substantially coplanar with an upper surface of “C” (inclusive of vias).
(claims 4 and 5) annotated Fig. 6B above; at least the distance of the curved right surface of “A” is less than the bottom surface of “C”.
(claim 6) Fig. 6B; a connection member including a second conductive pattern (256b) and a third conductive pattern (258b).
(claim 7) annotated Fig. 6B above; lowermost surface of “B” is less than a distance of the lowermost surface of 256b from the substrate 210.
(claim 9) Fig. 6B; a second signal pad (BP2).
(claim 10) annotated Fig. 6B above; an insulating layer (221); first and second wiring structures (222; left on “A” and right on “C”).
(claim 12) Fig. 6B; bonding layer (251b) and memory dies (200A, 200B1, 200B2, 200C) are free of a gap therebetween.
Regarding claims 13, 15 and 17, Choi discloses:
A semiconductor package (Figs. 6A/6B) comprising:
a buffer die (100);
memory dies (para 0062; 200A, 200B1, 200B2, 200C) sequentially stacked on the buffer die;
a conductive connection member between the memory dies, the conductive connection member including a first conductive pattern (256b) and a second conductive pattern (258b) stacked in a vertical direction substantially perpendicular to an upper surface of the buffer die (see Fig. 6A in view of Fig. 6B), and the first and second conductive patterns including different materials (paras 0035 and 0036; copper or alloys including the same) from each other;
a bonding layer (251b) between the memory dies, wherein the bonding layer is configured to bond ones of the memory dies with each other; and
a molding member (260) on the buffer die, wherein the molding member is on sidewalls of the memory dies,
wherein each of the memory dies includes:
a substrate (210) having first (bottom) and second (top) surfaces opposite to each other in a vertical direction; and
a signal pad (see annotated Fig. 6B below; IOS portion “C”) and a test pad structure (ETS) on the first surface of the substrate,
wherein the test pad structure includes a test pad (see annotated Fig. 6B below; “A”) and a third conductive pattern (see annotated Fig. 6B below; “B”) stacked in the vertical direction on the first surface of the substrate, and
wherein the signal pad contacts the first conductive pattern of the conductive connection member; and
wherein a distance from the substrate to a lowermost surface of the third conductive pattern is less than a distance from the substrate to a lower surface of the first conductive pattern.
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(claim 15) annotated Fig. 6B above; bottom of test pad (“A”) having different distances from the substrate.
(claim 17) annotated Fig. 6B above; an insulating layer (221); first and second wiring structures (222; left on “A” and right on “C”).
Allowable Subject Matter
Claims 8, 11, 14, 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art fails to teach or clearly suggest the limitations of claim 8 stating “wherein a distance from the substrate to a lowermost surface of the first conductive pattern is greater than a distance from the substrate to a lower surface of the third conductive pattern”; of claim 11 stating “wherein the test pad structure further includes a seed pattern between the first conductive pattern and the test pad, and wherein the first conductive pattern includes a first portion and a second portion, wherein an upper surface and a sidewall of the first portion is overlapped by the seed pattern, and a lower surface and a sidewall of the second portion is overlapped by the bonding layer”; of claim 14 stating “wherein portions of a lower surface of the third conductive pattern have different respective distances from the substrate”; and of claim 16 stating “wherein a distance from the substrate to a lowermost surface of the test pad is less than a distance from the substrate to a lower surface of the signal pad”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention.
Claims 18-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
The prior art fails to teach or clearly suggest of claim 18 stating “wherein distance from the first substrate to a lowermost surface of the third conductive pattern is less than distance from the first substrate to a lower surface of the first conductive pattern”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
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/ERROL V FERNANDES/Primary Examiner, AU 2893
