DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
1. The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
2. This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) is/are: “configured to” in claims 1-20 “means” in claims 18-20.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-11, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over SRIVASTAVA (Pub. No. US 20240111354) in view of Ishiguro (US Patent US12591393)
As per claim 1, SRIVASTAVA discloses a data storage device (fig.1, endpoint device 112/250), comprising:
a memory device (fig.2, system memory 274); and
a controller (fig.2, PCIe controller 262) coupled to the memory device, wherein the controller is configured to: request to move one or more first lanes (paragraph 9, first set of lanes) of a first memory access controller (MAC) (Paragraph 44, it is known in the PCIe art that the MAC is part of the PCIe link 262, the link layer functions.) from a low power state (paragraph 56, a transition to a low power state (e.g., L0s or L1)) to a full operational state (paragraph 52, L0 represents an active state);
request to move one or more second lanes (paragraph 79, lines 3-4, a second set of lanes) of a second MAC from the full operational state to the low power state (paragraph 56, a transition to a low power state (e.g., L0s or L1)), wherein the second MAC is distinct from the first MAC (Paragraph 44, it is known in the PCIe art that the MAC is part of the PCIe controller 262 with second set of lanes vs first set of lanes as the link layer functions);
move the one or more second lanes (paragraph 79, lines 3-4, a second set of lanes) of the second MAC to the low power state (Paragraph 47, switch the link 285 between a partial width link state (e.g., L0p) and a standby state (e.g., L0ps) in FLIT mode without going through a recovery state); and
move the one or more first lanes (paragraph 79, lines 3-4, a second set of lanes) of the first MAC to the full operational state. (paragraph 52, L0 represents an active state), wherein the one or more first lanes (paragraph 9, first set of lanes) and the one or more second lanes (paragraph 79, lines 3-4, a second set of lanes) are the same lanes. (Paragraph 47, switch different set lanes between a partial width link state (e.g., L0p))
SRIVASTAVA discloses all the limitations as the above but does not explicitly discloses inform the second MAC that the one or more second lanes are in the low power state while the one or more second lanes are detached from the second MAC; connect the one or more second lanes to the first MAC; indicate to the first MAC that the one or more second lanes are available for full operational state while maintaining, for the second MAC, the indication that the one or more second lanes are in the low power state. However, Ishiguro discloses this (col.2, lines 11-14, The controller determines lanes to be set to an operating state among a plurality of lanes of a link between the host and the memory system, based on first information on one or more commands issued by the host. The controller sets the determined lanes among the plurality of lanes to the operating state. The controller sets lanes other than the determined lanes among the plurality of lanes to a low power consumption state.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Ishiguro with the teaching of SRIVASTAVA so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 2, SRIVASTAVA discloses wherein the data storage device is configured to be coupled to a plurality of hosts, wherein controller comprises a lane management module that includes a plurality of physical layer (PHY) detaches and a plurality of MAC detaches (paragraph 69, a PCIe link, with multiple duplex lanes, the link 1002 are coupled to a link interface 1020 (e.g., PCIe interface) which provides a PHY level interface to the link 1002 and converts baseband signals to packets.)
As per claim 3, SRIVASTAVA discloses wherein a number of PHY detaches of the plurality of PHY detaches is equal to a number of hosts (fig.2, host clients 214) of the plurality of hosts (paragraph 31, Each of the one or more host clients 214 may be implemented on a processor executing software that performs the functions of the host clients 214 discussed herein.)
As per claim 4, SRIVASTAVA discloses wherein a number of MAC detaches of the plurality of MAC detaches is equal to a number of hosts (fig.2, host clients 214) of the plurality of hosts (paragraph 32, the PCIe interface circuit 216 is configured to transmit data (e.g., from the host clients 214) to the endpoint device system 250 over the PCIe link 285 and receive data from the endpoint device system 250 via the PCIe link 285.)
As per claim 5, SRIVASTAVA discloses wherein a number of PHY detaches of the plurality of PHY detaches is equal to a number of MAC detaches of the plurality of MAC detaches (paragraph 62, the width of the link 506 can be changed by controlling the number of lanes 511, 512, 513, 514 that are active and/or idle without interrupting the data flow.)
As per claim 6, SRIVASTAVA discloses wherein a PHY returns a message of “LOP ready” towards the second MAC after the request to move one or more second lanes of the second MAC from the full operational state to the low power state (Paragraphs 52-56, Fig. 4; Paragraphs 61-64, Fig. 5-7; L0 represents an active state, each of L1, L0s, and L0ps represent various levels of standby/idle/power save states).
As per claim 7, SRIVASTAVA discloses wherein a MAC detach is configured to communicate “LOP ready” to a MAC, to mimic PHY behavior. (Paragraphs 52-56, Fig. 4; Paragraphs 61-64, Fig. 5-7; L0 represents an active state, each of L1, L0s, and L0ps represent various levels of standby/idle/power save states).
As per claim 8, SRIVASTAVA discloses wherein the first MAC is configured to receive an indication from MAC detach logic that a Physical layer (PHY) state is still LOP (paragraph 48, the PHY TX block 266 may include logic for partitioning the data among the lanes.)
As per claim 9, SRIVASTAVA discloses wherein the controller is configured to connect the one or more second lanes to the first MAC. (Paragraphs 44 and 52; PCIe controller 262 of the PCIe interface circuit 260 and endpoint 250 may perform data link layer functions. It is known in the PCIe art that the MAC is part of the link layer.)
As per claim 10, SRIVASTAVA discloses wherein the controller is configured to sync up the one or more second lanes with a host device (paragraph 8, The controller is further configured to transition one or more lines of the second set of lanes PCIe link from the PLS to a partial width standby link state.)
As per claim 11, SRIVASTAVA discloses a data storage device (fig.1, endpoint device 112/250) comprising:
a memory device (fig.2, system memory 274); and
a controller (fig.2, PCIe controller 262) coupled to the memory device, wherein the controller is configured to: manage a plurality of lane (paragraph 9, set of lanes) connections between a plurality of memory access controllers (MACs) (Paragraph 44, it is known in the PCIe art that the MAC is part of the PCIe link 262, the link layer functions.) and a plurality of host devices (fig.2, host clients 214), wherein one or more first lane (paragraph 9, first set of lanes) connections of the plurality or lane (paragraph 79, lines 3-4, a second set of lanes) connections are present for a first MAC of the plurality of MACs (Paragraph 44, it is known in the PCIe art that the MAC is part of the PCIe link 262, the link layer functions), wherein one or more second lane (paragraph 79, lines 3-4, a second set of lanes) connections of the plurality of lane connections are present for a second MAC of the plurality of MACs(Paragraph 44, it is known in the PCIe art that the MAC is part of the PCIe link 262, the link layer functions.), and wherein one or more third lane connections (paragraph 79, lines 3-4, set of lanes) of the plurality of lane connections are shared by the first MAC and the second MAC (Paragraph 44, it is known in the PCIe art that the MAC is part of the PCIe link 262, the link layer functions);
cause the first MAC to register (paragraph 69, converts baseband signals to packets) the one or more third lane connections as being in a low power state (paragraph 56, a transition to a low power state (e.g., L0s or L1)); and cause the second MAC to register the one or more third lane connections as being in a full operational state (paragraph 52, L0 represents an active state), wherein the first MAC registers the one or more third lane connections as being in the low power state simultaneous with the second MAC registering the one or more third lane connections as being in the full operational state(Paragraph 53, Fig. 4; A link can return from L1 (standby state) to L0 (active state) via recovery state. Also, states L0s and L0ps can return to L0/L0p active state.)
SRIVASTAVA discloses all the limitations as the above but does not explicitly discloses inform the second MAC that the one or more second lanes are in the low power state while the one or more second lanes are detached from the second MAC; connect the one or more second lanes to the first MAC; indicate to the first MAC that the one or more second lanes are available for full operational state while maintaining, for the second MAC, the indication that the one or more second lanes are in the low power state. However, Ishiguro discloses this (col.2, lines 11-14, The controller determines lanes to be set to an operating state among a plurality of lanes of a link between the host and the memory system, based on first information on one or more commands issued by the host. The controller sets the determined lanes among the plurality of lanes to the operating state. The controller sets lanes other than the determined lanes among the plurality of lanes to a low power consumption state.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Ishiguro with the teaching of SRIVASTAVA so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 18, SRIVASTAVA discloses a data storage device (fig.1, endpoint device 112/250), comprising:
means to store data (fig.2, system memory 274); and
a controller (fig.2, PCIe controller 262) coupled to the means to store data, wherein the controller is configured to: maintain a physical layer (PHY )having a first plurality of lanes (paragraph 48, the PHY TX block 266 may include logic for partitioning the data among the lanes): maintain a first memory access controller (MAC that has a second plurality of lanes, wherein the first plurality is greater than the second plurality (paragraph 69, a PCIe link, with multiple duplex lanes, the link 1002 are coupled to a link interface 1020 (e.g., PCIe interface) which provides a PHY level interface to the link 1002 and converts baseband signals to packets);
maintain a second MAC that has a third plurality of lanes, wherein the first plurality is greater than the third plurality; and switch between a low power state and a full operational state (paragraph 52, L0 represents an active state) for lanes shared by the first MAC and the second MAC (paragraph 69, a PCIe link, with multiple duplex lanes, the link 1002 are coupled to a link interface 1020 (e.g., PCIe interface) which provides a PHY level interface to the link 1002 and converts baseband signals to packets).
SRIVASTAVA discloses all the limitations as the above but does not explicitly discloses inform the second MAC that the one or more second lanes are in the low power state while the one or more second lanes are detached from the second MAC; connect the one or more second lanes to the first MAC; indicate to the first MAC that the one or more second lanes are available for full operational state while maintaining, for the second MAC, the indication that the one or more second lanes are in the low power state. However, Ishiguro discloses this (col.2, lines 11-14, The controller determines lanes to be set to an operating state among a plurality of lanes of a link between the host and the memory system, based on first information on one or more commands issued by the host. The controller sets the determined lanes among the plurality of lanes to the operating state. The controller sets lanes other than the determined lanes among the plurality of lanes to a low power consumption state.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Ishiguro with the teaching of SRIVASTAVA so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 19, SRIVASTAVA discloses wherein the first plurality is less than a sum of the second plurality and the third plurality (paragraph 69, a PCIe link, with multiple duplex lanes, the link 1002 are coupled to a link interface 1020 (e.g., PCIe interface) which provides a PHY level interface to the link 1002 and converts baseband signals to packets).
As per claim 20, SRIVASTAVA discloses wherein the switching comprises switching from a full operational state for the shared lanes to a low power state for the first MAC(Paragraphs 44 and 52, performs the detection of a condition to transition the lanes to different power states), wherein the switching comprises switching from the lower power state to the full operational state for the shared lanes for the second MAC (paragraph 47, the host system 210 and endpoint system 250 can operate the PCIe link 285 in FLIT mode and switch the link 285 between a partial width link state (e.g., L0p) and a standby state.)
5. Claims 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over SRIVASTAVA (Pub. No. US 20240111354) in view of in view of Ishiguro (US Patent US12591393) and further in view of Chen et al. (Pub. No. US2019/0251055)
As per claim 12, SRIVASTAVA in view of Ishiguro disclose all the limitations as the above but does not explicitly disclose wherein the controller is configured to virtually connect the one or more lane (e.g., I/O lanes) connections to the second MAC. However, Chen discloses this. (paragraph 62, lines 8-10, a virtual hot plug event to the new root space PCIe controller to indicate the hot add, and the OS/BIOS associated with the new root space may respond by training the physical layer I/O lanes and start up traffic to configure the endpoint device(s))
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Chen with the teaching of SRIVASTAVA in view of Ishiguro so as for providing same technical field with respective virtually algorithm would enhance the system of SRIVASTAVA in view of Ishiguro to increase more functionality.
As per claim 13, Chen discloses wherein the controller is configured to virtually disconnect the one or more third lane connections from the first MAC. (paragraph 62, lines 1-3, to switch lane assignments between root spaces may include the PMC 612 first generating a virtual hot plug event to the root space PCIe controller that currently controls the physical layer I/O lanes)
As per claim 14, SRIVASTAVA discloses wherein the controller is configured to cause the first MAC to register connection to the one or more first lane connections and the one or more third lane connections with the first MAC registering the one or more first lane connections as in the full operational state and the one or more third lane connections in the low power state (paragraph 71, managing PCIe power 1040 and to transmit line state registers 1042 and receive line state registers 1044.)
As per claim 15, SRIVASTAVA discloses wherein the controller is configured to cause the second MAC to register connection to the one or more second lane connections and the one or more third lane connections with the second MAC registering the one or more second lane connections and the one or more third lane connections as in the full operational state (Paragraph 53, Fig. 4; A link can return from L1 (standby state) to L0 (active state) via recovery state. Also, states L0s and L0ps can return to L0/L0p active state.)
As per claim 16, SRIVASTAVA discloses wherein the first MAC is coupled to a lane management module that has a corresponding first MAC detach and a PHY detach, and wherein the PHY detach is coupled to a multi-lane PHY. (Paragraphs 52-56, Fig. 4; Paragraphs 61-64, Fig. 5-7; L0 represents an active state, each of L1, L0s, and L0ps represent various levels of standby/idle/power save states).
As per claim 17, SRIVASTAVA discloses wherein the lane management module is configured to detach lanes from a first interface with MAC A and to detach lanes from a second interface with MAC B (paragraph 69, a PCIe link, with multiple duplex lanes, the link 1002 are coupled to a link interface 1020 (e.g., PCIe interface) which provides a PHY level interface to the link 1002 and converts baseband signals to packets).
Response to Amendment
6. Applicant's amendment filed on 8/7/2026 have been fully considered but are moot in view of the new ground(s) of rejection.
7. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Kasichainula [Pub. No. US20230098298] discloses the MAC 220 to enter into a valid, operational state, allowing data transfer to occur via the port.
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
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