Detailed Action
The instant application having Application No. 18/829,657 has a total of 17 claims pending in the application; there are 3 independent claims and 14 dependent claims, all of which are ready for examination by the examiner. This Office action is in response to the claims filed 9/10/24. Claims 1-17 are pending.
NOTICE OF PRE-AIA OR AIA STATUS
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant's drawings submitted 9/10/24 are acceptable for examination purposes.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 14 recites the limitation of “The memory system of claim 13, wherein when the data to be read is invalid, the memory controller is configured to read data predicted to be requested by the host from the nonvolatile memory.“ However, claim 13 recites “and read, when the read to be read is valid, the data from the nonvolatile memory.” Therefore it appears that the data is being read on being both valid and invalid. Applicant’s specification, para. 111-112 appears to recite that invalid data is not read. Therefore it is unclear how both valid and invalid data is being read out in this situation.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10 and 16-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jung et al. (U.S. Patent Application Publication No. 2024/0402945), herein referred to as Jung et al.
Referring to claim 1, Jung et al. disclose as claimed, a memory system comprising: a nonvolatile memory; and a memory controller connectable to a host and configured to control the nonvolatile memory (see fig. 1, showing a host 100 connectable to a memory controller 210 containing non-volatile memory 220), wherein the memory controller has a speculative reading mode of reading in advance data predicted to be requested by the host from the nonvolatile memory (see para. 98-102, where a prefetch analyzer determines when read commands are consecutive and uses file fragment information to prefetch advance data predicted to be requested by the host. See para. 75, where this fragmentation information allows a prefetch hit rate and sequential read performance to be improved), the memory controller is configured to record a physical address indicating a physical location of the nonvolatile memory at which data that is last requested to be read by the host is stored (see para. 94-97, where it is determined if read commands have consecutive addresses. Therefore the last requested physical address is stored in order to compare it to the next data request), determine, when the host requests data to be read, whether or not to transition to the speculative reading mode, based on a physical address of the nonvolatile memory at which the requested data is stored and the recorded physical address (see para. 94-99, where it is determined if read commands have consecutive addresses. Therefore the last requested physical address is stored in order to compare it to the next data request. It is then determined whether to process the read commands without prefetching or to transition to prefetch mode. Also see fig. 12) , and transition, when determining to transition to the speculative reading mode, to the speculative reading mode, and read, from the nonvolatile memory, data in a range determined with respect to a physical address associated with a logical address specified by the host (see para. 34, 46, where a read command from a host may include information about a LUN of the storage device or an LBA. See para. 94-99, where it is determined to transition to prefetch mode and read data in the determined range).
Claims 16 and 17 recite similar limitations to claim 1 and would be rejected using the same rationale.
As to claim 2, Jung et al. also disclose the memory system of claim 1, wherein when the physical address of the nonvolatile memory at which the data requested by the host is stored continues to be an address that is larger than the recorded physical address by a size of a data reading unit by the host a preset number of times, the memory controller is configured to determine to transition to the speculative reading mode (see para. 98, where if r number of read commands are consecutive, then a prefetch mode is activated. R would be a preset number of times that data is larger by a size or consecutive than the previous data).
As to claim 3, Jung et al. also disclose the memory system of claim 1, wherein when the physical address of the nonvolatile memory at which the data requested by the host is stored continues to be an address in a range determined with respect to the recorded physical address a preset number of times, the memory controller is configured to determine to transition to the speculative reading mode (see para. 94-99, where it is determined if read commands have consecutive addresses. Therefore the last requested physical address is stored in order to compare it to the next data request. It is then determined whether to process the read commands without prefetching or to transition to prefetch mode. Also see fig. 12. see para. 98, where if r number of read commands are consecutive, then a prefetch mode is activated. R would be a preset number of times that data is larger by a size or consecutive than the previous data. Therefore R-> R+ the first address would constitute a range. In the example given of R=3, 3 consecutive hits in that range would trigger a transition to prefetch or speculative reading mode).
As to claim 4, Jung et al. also disclose the memory system of claim 3, wherein the memory controller is configured to determine whether or not the physical address of the nonvolatile memory at which the data requested by the host is stored is larger than the recorded physical address (see para. 94-97, where it is determined if read commands have consecutive addresses. Therefore it is determined if the next address would be larger, as a next consecutive address would be an address increased by a read size); update, when the physical address of the nonvolatile memory at which the data requested by the host is stored is larger than the recorded physical address, the recorded physical address to the physical address of the nonvolatile memory at which the data requested by the host is stored; and omit, when the physical address of the nonvolatile memory at which the data requested by the host is stored is not larger than the recorded physical address, to update the recorded physical address (see para. 94-97, where it is determined if read commands have consecutive addresses. Therefore it is determined if the next address would be larger, as a next consecutive address would be an address increased by a read size. See para. 98, where any number of consecutive read commands may be kept track of. Therefore, the number and addresses of read commands are updated after each host request. If a host request is not consecutive, then the number of previous consecutive requests and addresses would not be updated and would need to be reset to zero).
As to claim 5, Jung et al. also disclose the memory system of claim 4, wherein when the physical address of the nonvolatile memory at which the data requested by the host is stored is larger than the recorded physical address, the memory controller is configured to determine whether or not a difference between the physical address of the nonvolatile memory at which the data requested by the host is stored and the recorded physical address is less than or equal to a threshold value (see para. 94-97, where it is determined if read commands have consecutive addresses. Therefore it is determined if the next address would be larger, as a next consecutive address would be an address increased by a read size. Para. 98, mentions comparing a first read address and a chunk size to a second address. Therefore the threshold value would be the chunk size); update, when the difference is less than or equal to the threshold value, the recorded physical address to the physical address of the nonvolatile memory at which the data requested by the host is stored; and omit, when the difference exceeds the threshold value, to update the recorded physical address (see para. 94-97, where it is determined if read commands have consecutive addresses. Therefore it is determined if the next address would be larger, as a next consecutive address would be an address increased by a read size. See para. 98, where any number of consecutive read commands may be kept track of. Therefore, the number and addresses of read commands are updated after each host request. If a host request is not consecutive, then the number of previous consecutive requests and addresses would not be updated and would need to be reset to zero).
As to claim 6, Jung et al. also disclose the memory system of claim 1, wherein the nonvolatile memory includes blocks each including pages (see para. 33, where the non-volatile memory may be a NAND flash memory for example, which contains blocks and pages), and the memory controller is configured to perform, when the host requests data to be written, writing into the nonvolatile memory to store a logical address specified by the host in a first area of the pages and to store data received from the host in a second area of the pages (see para. 159, where a flash conversion layer may perform functions such as address mapping, which would store logical addresses specified by the host. See para. 32 and 148-158, where data is written to a non volatile memory, which would store data from the host ), and determine, in the speculative reading mode, whether or not to continue the speculative reading mode, based on the logical address specified by the host and a logical address read from the nonvolatile memory together with the data predicted to be requested by the host (see para. 94-99, where it is determined if read commands have consecutive addresses. Therefore the last requested physical address is stored in order to compare it to the next data request. It is then determined whether to process the read commands without prefetching or to transition to prefetch mode. Also see fig. 12).
As to claim 7, Jung et al. also disclose the memory system of claim 6, wherein in the speculative reading mode, the memory controller is configured to determine, when the logical address specified by the host matches the logical address read from the nonvolatile memory together with the data predicted to be requested by the host in a case where the host requests data to be read, to continue the speculative reading mode (see fig. 14, showing multiple host requests pointing to addresses that were previously prefetched. The speculative reading or prefetch mode continues as long as the addresses are consecutive. See fig. 12 ).
As to claim 8, Jung et al. also disclose the memory system of claim 6, wherein in the speculative reading mode, the memory controller is configured to read, from the nonvolatile memory, data stored at a location indicated by an address that is larger than the physical address associated with the logical address specified by the host by a size of a data reading unit by host (see para. 130, where the host may transmit the rad command, and a prefetch stream may be generated with prefetch size of 512KB, then addresses 2048-3332 are read).
As to claim 9, Jung et al. also disclose the memory system of claim 6, wherein in the speculative reading mode, the memory controller is configured to determine whether or not the physical address associated with the logical address specified by the host is larger than the recorded physical address (see para. 94-97, where it is determined if read commands have consecutive addresses. Therefore it is determined if the next address would be larger, as a next consecutive address would be an address increased by a read size); update, when the physical address associated with the logical address specified by the host is larger than the recorded physical address, the recorded physical address to the physical address associated with the logical address specified by the host, and read data in a part of a range determined with respect to the updated physical address from the nonvolatile memory (see para. 98, where it is determined if an address is larger (consecutive addresses), and then prefetching mode is enabled. See para. 101-103, where a range of prefetching is determined based on file fragments, and the prefetched data in that range is then read), the part of the range determined with respect to the updated physical address not overlapping a range determined with respect to the pre-update physical address (see fig. 15 for example, where ranges of prefetched data do not overlap); and omit, when the physical address associated with the logical address specified by the host is not larger than the recorded physical address, to update the recorded physical address (see para. 94-97, where it is determined if read commands have consecutive addresses. Therefore it is determined if the next address would be larger, as a next consecutive address would be an address increased by a read size. See para. 98, where any number of consecutive read commands may be kept track of. Therefore, the number and addresses of read commands are updated after each host request. If a host request is not consecutive, then the number of previous consecutive requests and addresses would not be updated and would need to be reset to zero).
As to claim 10, Jung et al. also disclose the memory system of claim 9, wherein when the physical address associated with the logical address specified by the host is larger than the recorded physical address, the memory controller is configured to determine whether or not a difference between the physical address associated with the logical address specified by the host and the recorded physical address is less than or equal to a threshold value (see para. 94-97, where it is determined if read commands have consecutive addresses. Therefore it is determined if the next address would be larger, as a next consecutive address would be an address increased by a read size. Para. 98, mentions comparing a first read address and a chunk size to a second address. Therefore the threshold value would be the chunk size), update, when the difference is less than or equal to the threshold value, the recorded physical address to the physical address associated with the logical address specified by the host, and read data in a part of a range determined with respect to the updated physical address from the nonvolatile memory (see para. 98, where it is determined if an address is larger (consecutive addresses), and then prefetching mode is enabled. See para. 101-103, where a range of prefetching is determined based on file fragments, and the prefetched data in that range is then read. The threshold value would be a chunk size), the part of the range determined with respect to the updated physical address not overlapping a range determined with respect to the pre-update physical address (see fig. 15 for example, where ranges of prefetched data do not overlap); and omit, when the difference exceeds the threshold value, to update the recorded physical address (see para. 94-97, where it is determined if read commands have consecutive addresses. Therefore it is determined if the next address would be larger, as a next consecutive address would be an address increased by a read size. See para. 98, where any number of consecutive read commands may be kept track of. Therefore, the number and addresses of read commands are updated after each host request. If a host request is not consecutive, then the number of previous consecutive requests and addresses would not be updated and would need to be reset to zero).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. in view of Ishihara et al. (U.S. Patent Application Publication No. 2017/0199817), herein referred to as Ishihara et al.
As to claim 11, Jung et al. disclose the claimed invention except for the memory system of claim 1, wherein the memory controller is configured to manage a correspondence table indicating whether data stored in the nonvolatile memory is valid or invalid, and determine, in the speculative reading mode, when data of the logical address specified by the host is read in advance from the nonvolatile memory as the data predicted to be requested by the host, whether or not the read data is valid or invalid, based on the correspondence table, and transmit, when the read data is valid, the read data to the host.
However, Ishihara et al. disclose wherein the memory controller is configured to manage a correspondence table indicating whether data stored in the nonvolatile memory is valid or invalid (see para. 56-57, where the validity of data is determined by an expiration date. See para. 93, where a valid flag in the device management information is activated or deactivated depending on the expiration date. Also see para. 78-81, where entries in tables show expiration dates which determine validity), and determine, in the speculative reading mode, when data of the logical address specified by the host is read in advance from the nonvolatile memory as the data predicted to be requested by the host, whether or not the read data is valid or invalid, based on the correspondence table, and transmit, when the read data is valid, the read data to the host (see para. 78, where it is determined if data is not expired and present. See para. 56-57, where on a data read, it is determined if the data is valid by looking at the expiration date. See fig. 15, showing that data is not read if it is not present/valid).
Jung et al. and Ishihara et al. are analogous art because they are from the same field of endeavor of data storage (see Jung et al., abstract and Kim, abstract, regarding memory and data storage).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jung et al. to comprise wherein the memory controller is configured to manage a correspondence table indicating whether data stored in the nonvolatile memory is valid or invalid, and determine, in the speculative reading mode, when data of the logical address specified by the host is read in advance from the nonvolatile memory as the data predicted to be requested by the host, whether or not the read data is valid or invalid, based on the correspondence table, and transmit, when the read data is valid, the read data to the host., as taught by Ishihara et al., in order to free up space for data that is no longer useful by having an expiration date.
As to claim 12, Jung et al. and Ishihara et al. also disclose the memory system of claim 11, wherein the memory controller is configured to read and output the data predicted to be requested by the host to a cache memory having a ring buffer structure, and refer to the cache memory in descending order of physical addresses and retrieves data of the logical address specified by the host (see Ishihara et al., para. 115, where the data stored in the volatile storage device has a ring buffer and may be stored in descending order. See para. 86-87, where that data may be a cache memory).
As to claim 13, Jung et al. disclose the claimed invention except for the memory system of claim 1, wherein the memory controller is configured to manage a correspondence table indicating whether data stored in the nonvolatile memory is valid or invalid, and determine, when reading the data predicted to be requested by the host from the nonvolatile memory, whether or not the data to be read is valid or invalid, based on the correspondence table, and read, when the read to be read is valid, the data from the nonvolatile memory.
However, Ishihara et al. disclose the memory system of claim 1, wherein the memory controller is configured to manage a correspondence table indicating whether data stored in the nonvolatile memory is valid or invalid (see para. 56-57, where the validity of data is determined by an expiration date. See para. 93, where a valid flag in the device management information is activated or deactivated depending on the expiration date. Also see para. 78-81, where entries in tables show expiration dates which determine validity), and determine, when reading the data predicted to be requested by the host from the nonvolatile memory, whether or not the data to be read is valid or invalid, based on the correspondence table, and read, when the read to be read is valid, the data from the nonvolatile memory (see para. 78, where it is determined if data is not expired and present. See para. 56-57, where on a data read, it is determined if the data is valid by looking at the expiration date. See fig. 15, showing that data is not read if it is not present/valid).
Jung et al. and Ishihara et al. are analogous art because they are from the same field of endeavor of data storage (see Jung et al., abstract and Kim, abstract, regarding memory and data storage).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jung et al. to comprise the memory system of claim 1, wherein the memory controller is configured to manage a correspondence table indicating whether data stored in the nonvolatile memory is valid or invalid, and determine, when reading the data predicted to be requested by the host from the nonvolatile memory, whether or not the data to be read is valid or invalid, based on the correspondence table, and read, when the read to be read is valid, the data from the nonvolatile memory, as taught by Ishihara et al., in order to free up space for data that is no longer useful by having an expiration date.
14. As to claim 14, Jung et al. and Ishihara et al. also disclose the memory system of claim 13, wherein when the data to be read is invalid, the memory controller is configured to read data predicted to be requested by the host from the nonvolatile memory (see 112 rejection above. In light of that, this is interpreted as data is not being read when it is found to be invalid. See Ishihara et al., para. 78, where it is determined if data is not expired and present. See para. 56-57, where on a data read, it is determined if the data is valid by looking at the expiration date. See fig. 15, showing that data is not read if it is not present/valid).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. in view of Kim (U.S. Patent Application Publication No. 2024/0143192), herein referred to as Kim.
As to claim 15, Jung et al. also disclose the memory system of claim 1, wherein the nonvolatile memory includes blocks each including pages (see para. 33, where the non-volatile memory may be a NAND flash memory for example, which contains blocks and pages).
Jung et al. disclose the claimed invention except for the memory controller is configured to manage a list indicating an order of the blocks used to write data of the host, and is allowed to continue reading of the data predicted to be requested by the host over two blocks, based on the list.
However, Kim discloses the memory controller is configured to manage a list indicating an order of the blocks used to write data of the host, and is allowed to continue reading of the data predicted to be requested by the host over two blocks, based on the list (see para. 163, where a list is used to indicate the write order of blocks, and is managed by the memory controller. This also manages sequences which memory blocks are opened and closed, which would allow for reading data based on the list).
Jung et al. and Kim. are analogous art because they are from the same field of endeavor of memory (see Jung et al., abstract and Kim, abstract, regarding memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jung et al. to comprise wherein the memory controller is configured to manage a list indicating an order of the blocks used to write data of the host, and is allowed to continue reading of the data predicted to be requested by the host over two blocks, based on the list, as taught by Kim, in order to write data to blocks that may have less wear or more wear, depending on wear count, to extend the life of the memory by managing writes and erases.
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-17 have received a first action on the merits and are the subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALAN OTTO whose telephone number is (571)270-1626. The examiner can normally be reached on M-F 8:30AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.O/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
Prosecution Insights