DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3-6, 8-11, and 13-15 are pending.
The U.S.C. 112 rejections, other than those stated below, have been corrected and the rejections are withdrawn.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18829637 in view of Aldereguia et al. (US 20100325404).
Although the claim 1 at issue is not identical, is are not patentably distinct from each other because claims 1 of the instant application is obvious by copending application 18829637 claim 1 in that the copending application 18829637 contain all the limitations of the instant application in view of Aldereguia et al. (US 20100325404).
Aldereguia and copending Application 18829637 are both related to programming FPGAs. Aldereguia is cited to teach a similar concept of using voltages for (re)programming an FPGA or CPLD. Aldereguia teaches disabling main power in response to a trigger for updating the FPGA/PLD. Based on Aldereguia, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified copending Application 18829637 to remove power in response to a trigger for reprogramming which allows the PLDs to be updated by removing the standby power. Furthermore, being able to remove power in response to a trigger for reprogramming improves on Aldereguia by being able to ensure reprogramming will be successful. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because to ensure reprogramming will be successful.
Instant Application 18829668
Application 18829637
Aldereguia et al. (US 20100325404)
Claim 1: An information handling system comprising: a processor; a logic device communicatively coupled to the processor and configured to perform a function to extend the functionality of the information handling system;
Claim 1: An information handling system comprising: a processor; a logic device communicatively coupled to the processor and configured to perform a function to extend the functionality of the information handling system;
a power system configured to generate a main power rail, wherein the main power rail is configured to be withdrawn by the power system in response to a trigger for updating functional logic of the logic device;
Figs. 2 and 4, [0021], “the primary compute node is assigned some additional responsibilities for triggering and monitoring the processes for updating PLDs according”, [0060], “The operation of out-of-band power control circuit (146), however, can completely remove all power from such PLDs, including standby power that would ordinarily be applied by the main power supply (137) under usual control by the main power control system (136). As long as external A/C power (130) is connected, the auxiliary rectifier and voltage regulator (133) provides power (134) to the timer (135), even when the main A/C power (132) to the compute node is gated off by the A/C gating transistor. When the primary compute node determines that all compute nodes, including the primary compute node, have successfully received the update of the configuration instructions, the primary compute node sends to all the compute nodes, out-of-band through bus (101) and the service processors (150), an instruction to power off for a predetermined period of time. The service processors deliver this instruction to the timers (135) which turn off their A/C gating transistors for the predetermined period of time, say 10 seconds, for example. …This completely cuts off all power to the main power supply (137), which in this mode cannot provide any D/C power (138) to components whatsoever, including standby power to PLDs. Upon expiration of the predetermined period, the timers (135) in each compute node operate their A/C gating transistors (131) to return main A/C power (132) to each compute node, booting the compute nodes in SMP mode, and thereby reconfiguring PLDs (155 on FIG. 1) according to their updated configuration instructions.”)
a voltage regulator configured to receive the main power rail and generate an auxiliary power rail for providing electrical energy to the logic device;
Figs. 1 and 5
and a discharge circuit electrically and communicatively coupled to the logic device, the discharge circuit comprising; a switching network configured to, in response to the trigger for updating functional logic of the logic device, discharge the main power rail;
a discharge circuit electrically and communicatively coupled to the logic device, the discharge circuit comprising: a switching network configured to, in response to a trigger for updating functional logic of the logic device, discharge a power rail for providing electrical energy to the logic device
and a monitoring circuit configured to, in response to the trigger for updating functional logic of the logic device :monitor a voltage on the auxiliary power rail; and responsive to the voltage falling below a threshold voltage: cause the switching network to cease discharging the main power rail; and enable completion of an update to the functional logic of the logic device.
and a monitoring circuit configured to: monitor a voltage on the power rail; and responsive to the voltage falling below a threshold voltage: cause the switching network to cease discharging the power rail; and enable completion of an update to the functional logic of the logic device.
Although the claims at issue is not identical, they are not patentably distinct from each other because claim 3 of the instant application is obvious by application 18829637 claim 2 in that the application 18829637 contain all the limitations of the instant application.
Although the claims at issue is not identical, they are not patentably distinct from each other because claim 4 of the instant application is obvious by application 18829637 claim 3 in that the application 18829637 contain all the limitations of the instant application.
Although the claims at issue is not identical, they are not patentably distinct from each other because claim 5 of the instant application is obvious by application 18829637 claim 4 in that the application 18829637 contain all the limitations of the instant application.
Although the claims at issue are not identical, they are not patentably distinct from each other because claim 11 of the instant application is obvious by instant application 18829637 claim 9 in that the application 18829637 in view of Aldereguia et al. (US 20100325404) contains all the limitations of the instant application.
Although the claims at issue is not identical, they are not patentably distinct from each other because claim 13 of the instant application is obvious by application 18829637 claim 10 in that the application 18829637 contain all the limitations of the instant application.
Although the claims at issue is not identical, they are not patentably distinct from each other because claim 14 of the instant application is obvious by application 18829637 claim 11 in that the application 18829637 contain all the limitations of the instant application.
Although the claims at issue is not identical, they are not patentably distinct from each other because claim 15 of the instant application is obvious by application 18829637 claim 12 in that the application 18829637 contain all the limitations of the instant application.
Claims 6, 8-10 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5-8 of copending Application No. 18829637
Although the claims at issue are not identical, they are not patentably distinct from each other because claim 6 of the instant application are anticipated by patent claim 5 in that the application 18829637 claims contain all the limitations of the instant application.
Although the claims at issue are not identical, they are not patentably distinct from each other because claim 8 of the instant application are anticipated by patent claim 6 in that the application 18829637 claims contain all the limitations of the instant application.
Although the claims at issue are not identical, they are not patentably distinct from each other because claim 9 of the instant application are anticipated by patent claim 7 in that the application 18829637 claims contain all the limitations of the instant application.
Although the claims at issue are not identical, they are not patentably distinct from each other because claim 10 of the instant application are anticipated by patent claim 8 in that the application 18829637 claims contain all the limitations of the instant application.
This is a provisional nonstatutory double patenting rejection.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“a logic device … configured to perform” in claim 1,
“a power system configured to generate” in claim 1,
Structure was found to support a logic device in paragraph [0025].
Structure was found to support a power system in paragraph [0026].
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1, 3-5, 11 and 13-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a power system configured to generate a main power rail wherein the main power rail is configured to be withdrawn by the power system”. It is unclear how a main power rail is generated or withdrawn. A power rail is a physical line that delivers power and it cannot be generated or withdrawn/removed by a power system. For examination purposes, “a power system configured to generate a main power rail wherein the main power rail is configured to be withdrawn by the power system” will be read as “a power system configured to generate power on a main power rail wherein the power on the main power rail is configured to be withdrawn by the power system”.
Claim 11 recites “withdrawing a main power rail by a power system”. It is unclear how a main power rail is withdrawn. A power rail is a physical line that delivers power and it cannot be withdrawn/removed by a power system. For examination purposes, “withdrawing a main power rail by a power system” will be read as “withdrawing the power from a main power rail by a power system”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-5, 11 and 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aldereguia et al. (US 20100325404) in view of Edwards et al. (US 7676606)
Regarding claim 1, Aldereguia teaches
An information handling system comprising: a processor;
a logic device communicatively coupled to the processor and configured to perform a function to extend the functionality of the information handling system; (Fig. 1 (CPU – 156) and (PLD – 155), [0060], “thereby reconfiguring PLDs (155 on FIG. 1) according to their updated configuration instructions.”, and [0005], “The exact use of any particular PLD changes from one computer design to another--as well as within any particular computer design from time to time. This is a particular strength of PLDs--that system designers can change their functions even within the same system over time as needs evolve or designs improve.” Updating the PLD with a new configuration/updated function , where the updated configuration/function is interpreted as performing a new/improved function which thereby extends the functionality)
a voltage regulator (power supply – 137) configured to receive the main power rail (main power - 132) and generate an auxiliary power rail (DC power – 138) for providing electrical energy to the logic device; and (Figs. 1 and 5)
a power system configured to generate a main power rail, wherein the main power rail is configured to be withdrawn by the power system in response to a trigger for updating functional logic of the logic device; (Figs. 2 and 4, [0021], “the primary compute node is assigned some additional responsibilities for triggering and monitoring the processes for updating PLDs according”, [0060], “The operation of out-of-band power control circuit (146), however, can completely remove all power from such PLDs, including standby power that would ordinarily be applied by the main power supply (137) under usual control by the main power control system (136). As long as external A/C power (130) is connected, the auxiliary rectifier and voltage regulator (133) provides power (134) to the timer (135), even when the main A/C power (132) to the compute node is gated off by the A/C gating transistor. When the primary compute node determines that all compute nodes, including the primary compute node, have successfully received the update of the configuration instructions, the primary compute node sends to all the compute nodes, out-of-band through bus (101) and the service processors (150), an instruction to power off for a predetermined period of time. The service processors deliver this instruction to the timers (135) which turn off their A/C gating transistors for the predetermined period of time, say 10 seconds, for example. The timers continue to operate for this power off period because they are powered by their auxiliary voltage regulators (133) which are always connected to their main external A/C power source (130) even when all other power to the compute node is cut off by the A/C gating transistor. This completely cuts off all power to the main power supply (137), which in this mode cannot provide any D/C power (138) to components whatsoever, including standby power to PLDs. Upon expiration of the predetermined period, the timers (135) in each compute node operate their A/C gating transistors (131) to return main A/C power (132) to each compute node, booting the compute nodes in SMP mode, and thereby reconfiguring PLDs (155 on FIG. 1) according to their updated configuration instructions.”)
a discharge circuit electrically and communicatively coupled to the logic device, the discharge circuit comprising a switching network configured to, in response to the trigger for updating functional logic of the logic device, discharge the main power rail; and ([0060], “The service processors deliver this instruction to the timers (135) which turn off their A/C gating transistors for the predetermined period of time … This completely cuts off all power to the main power supply (137), which in this mode cannot provide any D/C power (138) to components whatsoever, including standby power to PLDs. Upon expiration of the predetermined period, the timers (135) in each compute node operate their A/C gating transistors (131) to return main A/C power (132) to each compute node, booting the compute nodes in SMP mode, and thereby reconfiguring PLDs (155 on FIG. 1) according to their updated configuration instructions.”” And claim 4, “including removing standby power from the PLDs, and powering on in unison all the of the compute nodes in the SMP computer, booting the compute nodes in SMP mode, thereby reconfiguring the PLDs according to the updated configuration instructions.”)
Aldereguia teaches discharging power from a voltage regulator before reprogramming an FPGA or CPLD but does not specifically teach that the voltage is below a threshold.
Edwards teaches the discharge circuit further comprising a monitoring circuit configured to: monitor a voltage on the auxiliary power rail; and responsive to the voltage falling below a threshold voltage: (col. 5 lines 31-40, “monitoring module 300 may monitor FPGAs 202 to determine their current state of operation. One particular method of monitoring download status is to connect all of the status pins 203 to a common lead which is connected to a voltage source (V.sub.cc) … In the programmable state, FPGAs 202 drive their status pins 203 so that the voltage on the common lead is approximately ground or "low.", when the voltage is low or ground it is below a threshold)
cause the switching network to cease discharging the main power rail; and (Fig. 5 (504), the programming state maintains the voltage, where a particular voltage is applied therefore ceasing discharge from the operating mode voltage, col. 7, lines 24-26, “Monitoring module 300 holds FPGAs 202 in programmable mode at step 504. This step 504 prevents FPGAs 202 from transitioning into operating mode”)
enable completion of an update to the functional logic of the logic device. (Fig. 5 (518), programming is completed and enabled for operation)
Aldereguia and Edwards are both related to programming FPGAs. Edwards is cited to teach a similar concept of using voltages for (re)programming an FPGA or CPLD. Edwards teaches that the discharged voltage be below a threshold before (re)programming. Based on Edwards, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Aldereguia to check that a voltage is below a threshold before reprogramming. Furthermore, being able to check that a voltage is below a threshold before reprogramming improves on Aldereguia by being able to ensure reprogramming will be successful. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because to ensure reprogramming will be successful.
Regarding claim 3, Aldereguia teaches the discharge circuit further comprising a timer circuit configured to: initiate a timer in response to the trigger; and responsive to expiration of the timer, cause the switching network to cease discharging the main power rail. ([0060], “As long as external A/C power (130) is connected, the auxiliary rectifier and voltage regulator (133) provides power (134) to the timer (135), even when the main A/C power (132) to the compute node is gated off by the A/C gating transistor. When the primary compute node determines that all compute nodes, including the primary compute node, have successfully received the update of the configuration instructions, the primary compute node sends to all the compute nodes, out-of-band through bus (101) and the service processors (150), an instruction to power off for a predetermined period of time. The service processors deliver this instruction to the timers (135) which turn off their A/C gating transistors for the predetermined period of time, say 10 seconds, for example. The timers continue to operate for this power off period because they are powered by their auxiliary voltage regulators (133) which are always connected to their main external A/C power source (130) even when all other power to the compute node is cut off by the A/C gating transistor. This completely cuts off all power to the main power supply (137), which in this mode cannot provide any D/C power (138) to components whatsoever, including standby power to PLDs. Upon expiration of the predetermined period, the timers (135) in each compute node operate their A/C gating transistors (131) to return main A/C power (132) to each compute node, booting the compute nodes in SMP mode, and thereby reconfiguring PLDs (155 on FIG. 1) according to their updated configuration instructions.”)
Regarding claim 4, Aldereguia teaches wherein the logic device comprises a complex programmable logic device. ([0025], “PLDs amenable to updating according to embodiments of the present invention include a complex programmable logic device (`CPLD`), a field programmable gate array (`FPGA`),”)
Regarding claim 5, Aldereguia teaches wherein the logic device comprises a field-programmable gate array. ([0025], “PLDs amenable to updating according to embodiments of the present invention include a complex programmable logic device (`CPLD`), a field programmable gate array (`FPGA`),”)
As to claim 11, Aldereguia and Edwards teach this claim according to the reasoning provided in claim 1.
As to claim 13, Aldereguia and Edwards teach this claim according to the reasoning provided in claim 3.
As to claim 14, Aldereguia and Edwards teach this claim according to the reasoning provided in claim 4.
As to claim 15, Aldereguia and Edwards teach this claim according to the reasoning provided in claim 5.
Claim(s) 6, 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aldereguia and Edwards in view of Sharma et al. (US 20250076911).
Regarding claim 6, Aldereguia teaches
A discharge circuit configured to electrically and communicatively couple to a logic device, the discharge circuit comprising: a switching network configured to, in response to a trigger for updating functional logic of the logic device, discharge a main power rail received by a voltage regulator configured to generate an auxiliary power rail from the main power rail, the auxiliary power rail configured to provide electrical energy to the logic device, (Figs. 2 and 4, [0021], “the primary compute node is assigned some additional responsibilities for triggering and monitoring the processes for updating PLDs according”, [0060], “The operation of out-of-band power control circuit (146), however, can completely remove all power from such PLDs, including standby power that would ordinarily be applied by the main power supply (137) under usual control by the main power control system (136). As long as external A/C power (130) is connected, the auxiliary rectifier and voltage regulator (133) provides power (134) to the timer (135), even when the main A/C power (132) to the compute node is gated off by the A/C gating transistor. When the primary compute node determines that all compute nodes, including the primary compute node, have successfully received the update of the configuration instructions, the primary compute node sends to all the compute nodes, out-of-band through bus (101) and the service processors (150), an instruction to power off for a predetermined period of time. The service processors deliver this instruction to the timers (135) which turn off their A/C gating transistors for the predetermined period of time, say 10 seconds, for example. The timers continue to operate for this power off period because they are powered by their auxiliary voltage regulators (133) which are always connected to their main external A/C power source (130) even when all other power to the compute node is cut off by the A/C gating transistor. This completely cuts off all power to the main power supply (137), which in this mode cannot provide any D/C power (138) to components whatsoever, including standby power to PLDs. Upon expiration of the predetermined period, the timers (135) in each compute node operate their A/C gating transistors (131) to return main A/C power (132) to each compute node, booting the compute nodes in SMP mode, and thereby reconfiguring PLDs (155 on FIG. 1) according to their updated configuration instructions.” And claim 4, “including removing standby power from the PLDs, and powering on in unison all the of the compute nodes in the SMP computer, booting the compute nodes in SMP mode, thereby reconfiguring the PLDs according to the updated configuration instructions.”)
Aldereguia teaches discharging power from a voltage regulator before reprogramming an FPGA or CPLD but does not specifically teach that the voltage is measured to be below a threshold.
Edwards teaches the discharge circuit further comprising a monitoring circuit configured to: monitor a voltage on the auxiliary power rail; and responsive to the voltage falling below a threshold voltage: (col. 5 lines 31-40, “monitoring module 300 may monitor FPGAs 202 to determine their current state of operation. One particular method of monitoring download status is to connect all of the status pins 203 to a common lead which is connected to a voltage source (V.sub.cc) … In the programmable state, FPGAs 202 drive their status pins 203 so that the voltage on the common lead is approximately ground or "low.", when the voltage is low or ground it is below a threshold)
cause the switching network to cease discharging the main power rail; and (Fig. 5 (504), the programming state maintains the voltage, where a particular voltage is applied therefore ceasing discharge from the operating mode voltage, col. 7, lines 24-26, “Monitoring module 300 holds FPGAs 202 in programmable mode at step 504. This step 504 prevents FPGAs 202 from transitioning into operating mode”)
enable completion of an update to the functional logic of the logic device. (Fig. 5 (518), programming is completed and enabled for operation)
Aldereguia and Edwards are both related to programming FPGAs. Edwards is cited to teach a similar concept of using voltages for (re)programming an FPGA or CPLD. Edwards teaches that the discharged voltage be below a threshold before (re)programming. Based on Edwards, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Aldereguia to check that a voltage is below a threshold before reprogramming. Furthermore, being able to check that a voltage is below a threshold before reprogramming improves on Aldereguia by being able to ensure reprogramming will be successful. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because to ensure reprogramming will be successful.
Aldereguia and Edwards teach a switch to disconnect power and discharge a rail but do not specifically teach the switch(es) include a connection between the power rail and ground.
Sharma teaches
wherein the switching network comprises one or more switches coupled between the main power rail and a ground voltage; and (Figs. 1 and 5, [0060], “The pull-down circuit may be configured, in response to a deactivation of the voltage regulator circuit, to couple a first resistor between the regulated power supply node and a ground supply node for a particular time period.” And [0050], “For example, in some embodiments, a variable resistance circuit may be implemented with multiple resistors and switches,”)
Aldereguia, Edwards, and Sharma are all related to discharging a power rail. Sharma is cited to teach a similar concept of discharging a voltage of a power rail when powered off by using switches connected to the power rail and ground. Based on Sharma, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Aldereguia and Edwards to discharge a voltage of a power rail when powered off by using switches connected to the power rail and ground. Furthermore, being able to discharge a voltage of a power rail when powered off by using switches connected to the power rail and ground improves on Aldereguia and Edwards by quickly discharge the power rail. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “By employing different pull-down resistance values at different times, a regulated power supply node may be rapidly discharged upon deactivation”, thereby reducing leakage, [0023]
As to claim 8, Aldereguia, Edwards, and Sharma teach this claim according to the reasoning provided in claim 3.
As to claim 9, Aldereguia, Edwards, and Sharma teach this claim according to the reasoning provided in claim 4.
As to claim 10, Aldereguia, Edwards, and Sharma teach this claim according to the reasoning provided in claim 5.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-6, 8-11, and 13-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 5/14/2026 have been fully considered but they are not persuasive for independent claim 1 and 11. The Applicant’s representative argues that Aldereguia fails to teach “a power system configured to generate a main power rail, wherein the main power rail is configured to be withdrawn by the power system in response to a trigger for updating” and “a switching network configured to, in response to the trigger for updating functional logic of the logic device, discharge the main power rail”. The Examiner respectfully disagrees to these assertions. Regarding the argument that the mail power rail is withdrawn in response to triggering, Aldereguia in paragraph [0060], “The operation of out-of-band power control circuit (146), however, can completely remove all power from such PLDs, including standby power that would ordinarily be applied by the main power supply (137) under usual control by the main power control system (136). As long as external A/C power (130) is connected, the auxiliary rectifier and voltage regulator (133) provides power (134) to the timer (135), even when the main A/C power (132) to the compute node is gated off by the A/C gating transistor … When the primary compute node determines that all compute nodes, including the primary compute node, have successfully received the update of the configuration instructions, the primary compute node sends to all the compute nodes, out-of-band through bus (101) and the service processors (150), an instruction to power off … Upon expiration of the predetermined period, the timers (135) in each compute node operate their A/C gating transistors (131) to return main A/C power (132) to each compute node, booting the compute nodes in SMP mode, and thereby reconfiguring PLDs (155 on FIG. 1) according to their updated configuration instructions.” As described in paragraph [0060], receive the trigger to turn off the main power supply once the reconfiguration information has been received. Once the timer expired, the power is resupplied thereby reconfiguring the logic. All of the limitations are met. Regarding the limitation of the switching network, paragraph [0060] as recited above, teach switches which are triggered to remove power and repower the system based on a timeout trigger which causes the reconfiguration of the PLD. Therefore these arguments are not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHERI L. HARRINGTON whose telephone number is (571)270-0468. The examiner can normally be reached Generally, M-F, 7:30a-4p.
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/CHERI L HARRINGTON/ Examiner, Art Unit 2176
July 24, 2026
/JAWEED A ABBASZADEH/ Supervisory Patent Examiner, Art Unit 2176
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