DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed in present Application filed on February 20, 2026.
Information Disclosure Statement
The information disclosure statements filed September 10,2024 have been submitted for consideration by the Office. It has been placed in the application file and the information referred to therein has been considered.
Applicants must continue to submit prior art references throughout the patent application process. A supplemental IDS must be submitted if prior art is discovered through a foreign patent application or an International Patent Search, or a related application before a prosecution closes.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Rejection of claim 1, the limitation “a through-via passing through the inorganic substrate” is indefinite or unclear. a through-via appears to be a through-via conductor.
Please clarify.
Rejection of claims 2-16, claims 2-16 are rejected by the same reason applied to rejection of claim 1 above.
Rejection of claim 9, the limitation “wherein the first insulating layer is integrated with at least one of the second insulating layer or the third insulating layer without an interlayer boundary” is indefinite or unclear.
Note that the first insulating layer, second insulation layer, and third insulation layer are different from each other therefore, each must have boarder; and claim 1 clearly states a second insulating layer disposed on the upper surface of the inorganic substrate and a third insulating layer disposed on the lower surface of the inorganic substrate and a lower surface of the first insulating layer; therefore, it can not be borderless. If the first insulating layer, second insulation layer, and third insulation layer are integrated as borderless; then it is only a single insulating layer with three different regions, not three different layers. See similar terminology; a first window or book with a first size adjacent to a second window or book with a second size are different structurally then a big window or book having the first window or book size and the second window or book size with no boundary(see for example reference US7462784 wherein 50 in fig. 11 and figs. 14-17 considered to be three layers with no real structural boarders but defining imaginary boarders exactly as current invention). It appears to be irrational.
Based on specification and figures presented, It is appears that claim and specification is misleading; and what is use of a first insulating layer covering at least a portion of an external surface of the inorganic substrate which is not upper or lower surface of the inorganic substrate because imaginary boundary are not real boundary of any layers of the entire board which can be easily manipulated by user need, and can not be consider real part of product. Product is what it is not how it is made by different process or how it is been used.
For more clarification, If the board has a single layer with three regions then define claim precisely as that; if the board has three different layers, please define clear boundary. Note that invention should support the main reason or intention of the invention.
Appropriate action is required.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AlA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7, 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Naganuma et al. (US20130025914, herein referred to as Naganuma).
Rejection of claim 1, Naganuma (figure 36 of Naganuma) discloses a printed circuit board comprising:
an inorganic substrate (200, see paragraph 0093).
a through via conductor (230) passing through the inorganic substrate (a through via 200 );
a first insulating layer (100) covering at least a portion of an external surface of the inorganic substrate (see external surface of 200) which is not upper or lower surface of the inorganic substrate;
a second insulating layer (301) disposed on the upper surface of the inorganic substrate (an upper surface of 200) and an upper surface of the first insulating layer (an upper surface of 100); a third insulating layer (302) disposed on the lower surface of the inorganic substrate (a lower surface of 200) and a lower surface of the first insulating layer (a lower surface of 100);
a first wiring layer (311) disposed on a portion of an upper surface of the second insulating layer (an upper surface of 301); and a second wiring layer disposed on a portion of a lower surface of the third insulating layer (a lower surface of 302, wiring layer 312),
and the inorganic substrate has an upper end and a lower end having different widths, in cross-section (see widths of 200 by having tapered sidewalls).
Examiner makes official notice that wherein the inorganic substrate includes ceramic or Silicon because ceramics provides high thermal conductivity, excellent electrical insulation, dimensional stability, low thermal expansion, and/or resistance to chemicals. Ceramic substrate dissipate heat far more efficiently than FR4 Board as well as low dielectric loss and stable dielectric constant for highly suitable for high frequency circuit; or Silicon for semiconductor component or device integration in the board.
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the printed circuit board of Naganuma to have inorganic substrate made of material for the reason given in the examiner official notice above.
Rejection of claim 2, Naganuma discloses the printed circuit board of claim 1, wherein the width of the upper end of the inorganic substrate is narrower than the width of the lower end of the inorganic substrate, in cross-section, and the external surface of the inorganic substrate is substantially inclined (see the external surface of 200 in figure 36 of Naganuma).
Rejection of claim 7, Naganuma discloses the printed circuit board of claim 1, The printed circuit board of claim 1, wherein the first to third insulating layers include an organic insulating material (see paragraph 0094 of Naganuma).
Rejection of claim 10, Naganuma discloses the printed circuit board of claim 1, further comprising: a first connection via passing through the second insulating layer, the first connection via connecting the through-via and the first wiring layer to each other; and a second connection via passing through the third insulating layer, the second connection via connecting the through-via and the second wiring layer to each other (see via in 301 and 302 connected via 230 with 311 and 312in figure 36 of Naganuma).
Rejection of claim 11, Naganuma discloses the printed circuit board of claim 1, further comprising: a third wiring layer disposed on the upper surface of the inorganic substrate, connected to the through-via, and at least partially buried in the second insulating layer; a fourth wiring layer disposed on the lower surface of the inorganic substrate, connected to the through-via, and at least partially buried in the third insulating layer; a first connection via passing through the second insulating layer, the first connection via connecting the first wiring layer and the third wiring layer to each other; and a second connection via passing through the third insulating layer, the second connection via connecting the second wiring layer and the fourth wiring layer to each other (see wiring layers connected to via 331b and 332b at F1 and F2 in figure 36 of Naganuma) .
Rejection of claim 12, Naganuma discloses the printed circuit board of claim 11, further comprising: one or more intermediate insulating layers disposed between the inorganic substrate and the second insulating layer; one or more intermediate wiring layers disposed on or in the one or more intermediate insulating layers; and one or more intermediate via layers passing through at least one of the one or more intermediate insulating layers, wherein the first insulating layer further covers at least a portion of an external surface of each of the one or more intermediate insulating layers (see structural area between 301 and 200 in figure 36 of Naganuma which discloses one intermediate insulating layer with a wiring layer and a via disposed between the inorganic substrate and the second insulating layer, and externally covered by 100 ).
Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Naganuma and Chujo et al. (US20080083558, herein referred to as Chujo).
Rejection of claim 3, Naganuma discloses the printed circuit board of claim 1, but fails to disclose further comprising: an inorganic insulating film covering at least a portion of each of the upper surface and the lower surface of the inorganic substrate, wherein the external surface of the inorganic substrate is spaced apart from the inorganic insulating film, and the external surface of the inorganic substrate is in contact with the first insulating layer.
Chujo discloses an inorganic insulating film (5-6 in figures 1-3, 5, 8) covering at least a portion of each of the upper surface and the lower surface of the inorganic substrate (2), wherein the external surface of the inorganic substrate is spaced apart from the inorganic insulating film, and the external surface of the inorganic substrate is in contact with the first insulating layer (see figures 1-3 of Chujo).
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the printed circuit board of Naganuma to have inorganic insulating film as taught by Chujo so that It will increase insulation and provide protection as well as circuit integrity between conductive layers. Additionally, It do provide board which has a high degree of freedom of wiring design and can realize high-density wiring, and a method which can simply manufacture the multilayer wiring board.
Rejection of claim 4, Naganuma in view of Chujo disclose the printed circuit board of claim 1, The printed circuit board of claim 3, wherein the inorganic insulating film includes an oxide film disposed on the inorganic substrate, and a nitride film disposed on the oxide film (see specification wherein insulation layer 6 made of silicone oxide while barrier layer 5 made of titanium nitride in Chujo ).
Rejection of claim 5, Naganuma in view of Chujo disclose the printed circuit board of claim 3, wherein the inorganic substrate has a through-hole in which the through-via conductor is disposed, and the inorganic insulating film extends to a space between the inorganic substrate and the through-via to further cover at least a portion of a wall surface of the through-hole (see figures of Chujo wherein 5-6 between through hole via conductor and substrate 2).
Rejection of claim 6, Naganuma in view of Chujo disclose the printed circuit board of claim 5, wherein the through-via includes a first metal layer disposed on the inorganic insulating film in the through-hole, and a second metal layer filling at least a portion of the through-hole, on the first metal layer, the second metal layer having a width wider than that of the first metal layer, in cross-section (see figures 5 and 8 of Chujo wherein first metal layer 7 disposed on the inorganic insulating film 5-6 in the through-hole, and second metal layer 8 filling at least a portion of the through-hole wider than first metal layer 7) .
Claims 8 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Naganuma and Kambe et al. (US20050263867, herein referred to as Kambe).
Rejection of claim 8, Naganuma discloses the printed circuit board of claim 7, wherein the first insulating layer has an interlayer boundary with each of the second insulating layer and the third insulating layer, and the upper surface and the lower surface of the first insulating layer are substantially coplanar with the upper surface and the lower surface of the inorganic substrate, respectively.
Kambe discloses wherein the first insulating layer has an interlayer boundary with each of the second insulating layer (102 next to a upper surface of a core sub section 1, figure 3 of Kambe) and the third insulating layer (102 next to a bottom surface of the core sub section 1), and the upper surface and the lower surface of the first insulating layer ( a core main body 100) are substantially coplanar with the upper surface and the lower surface of the inorganic substrate (the core sub section 1), respectively.
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the printed circuit board of Naganuma to have arrangement of insulating layers as taught by Kambe so that It will to provide an intermediate substrate which is substantially immune from disconnection by thermal stress, which lowers overall height of the substrate connection structure, and which reduces the number of connection steps. And/or the core main body formed in a plate, and accommodated in the sub-core compartment so as to be matched with the core main body in the thickness direction, therefore, easy to place insulating layers on top and bottom of core main body and the sub-core compartment and help to reduces manufacturing processes and cost.
Rejection of claim 13, Naganuma discloses the printed circuit board of claim 1, but fails to disclose one or more first build-up insulating layers disposed on an upper surface of the second insulating layer; one or more first build-up wiring layers disposed on or in the one or more first build-up insulating layers; one or more first build-up via layers passing through at least one of the one or more first build-up insulating layers; one or more second build-up insulating layers disposed on the lower surface of the third insulating layer; one or more second build-up wiring layers disposed on or in the one or more second build-up insulating layers; one or more second build-up via layers passing through at least one of the one or more second build-up insulating layers; a first resist layer disposed on an upper surface of an uppermost first build-up insulating layer among the one or more first build-up insulating layers, the first resist layer covering at least a portion of an uppermost first build-up wiring layer among the one or more first build-up wiring layers; a second resist layer disposed on a lower surface of a lowermost second build-up insulating layer among the one or more second build-up insulating layers, the second resist layer covering at least a portion of a lowermost second build-up wiring layer among the one or more second build-up wiring layers, wherein the first resist layer has a plurality of first openings exposing at least a portion of the uppermost first build-up wiring layer, and the second resist layer has a plurality of second openings exposing at least a portion of the lowermost second build-up wiring layer.
Kambe (figure 3) discloses one or more first build-up insulating layers disposed on an upper surface of the second insulating layer (see other one or more layers 102 on the top surface of a layer 102 next to sub core section 1, see figure 3 of Kambe); one or more first build-up wiring layers disposed on or in the one or more first build-up insulating layers (see the wiring layers 108 in or on the other layers 102); one or more first build-up via layers passing through at least one of the one or more first build-up insulating layers (see a via 107 in the other layers102); a first resist layer disposed on an upper surface of an uppermost first build-up insulating layer among the one or more first build-up insulating layers (a top resist layer 101), the first resist layer covering at least a portion of an uppermost first build-up wiring layer among the one or more first build-up wiring layers (see figure 3); and a second resist layer (a bottom resist layer 101) disposed on a lower surface of a lowermost second build-up insulating layer among the one or more second build-up insulating layers (one or more other layers 102 between a layer 102 next to a lower surface of sub core section 1 and the bottom resist layer 101), the second resist layer covering at least a portion of a lowermost second build-up wiring layer among the one or more second build-up wiring layers (see figure 3 of Kambe), wherein the first resist layer has a plurality of first openings exposing at least a portion of the uppermost first build-up wiring layer (see openings of the top resist layer 101), and the second resist layer has a plurality of second openings exposing at least a portion of the lowermost second build-up wiring layer (see openings of the top resist layer 101).
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the printed circuit board of Naganuma to have build up layers and resist layers with wiring layers as taught by Kambe so that mentions that resist layer layers are able to protect the built-up wiring layer from external physical and chemical damages and also work as solder resist, and have a plurality of openings for exposing at least a portion of the build-up wiring layer for electrical connection to other devices and furthermore, having build-up insulating layers so that accommodation of different wiring or circuit pattern layers and connection between the different wiring or circuit pattern layers through vias are possible as well as maintain electrical insulation to prevent any damage or short circuit between the different wiring or circuit pattern layers.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Naganuma and Hwang et al. (US20210183784, herein referred to as Hwang).
Rejection of claim 14, Naganuma discloses the printed circuit board of claim 1, but fails to disclose further comprising: one or more first build-up insulating layers disposed on an upper surface of the second insulating layer; one or more first build-up wiring layers disposed on or in the one or more first build-up insulating layers; one or more first build-up via layers passing through at least one of the one or more first build-up insulating layers; a first resist layer disposed on an upper surface of an uppermost first build-up insulating layer among the one or more first build-up insulating layers, the first resist layer covering at least a portion of an uppermost first build-up wiring layer among the one or more first build-up wiring layers; and a second resist layer disposed on the lower surface of the third insulating layer, the second resist layer covering at least a portion of the second wiring layer, wherein the first resist layer has a plurality of first openings exposing at least a portion of the uppermost first build-up wiring layer, and the second resist layer has a plurality of second openings exposing at least a portion of the second wiring layer.
Hwang (figure 8) discloses further comprising: one or more first build-up insulating layers disposed on an upper surface of the second insulating layer (see one or more layers on a layer on the top surface of 120, see figure 8); one or more first build-up wiring layers disposed on or in the one or more first build-up insulating layers (see one or more wiring layers in or on the one or more layers); one or more first build-up via layers passing through at least one of the one or more first build-up insulating layers (see one or more via layers in the one or more layers); a first resist layer disposed on an upper surface of an uppermost first build-up insulating layer among the one or more first build-up insulating layers (a resist layer 180), the first resist layer covering at least a portion of an uppermost first build-up wiring layer among the one or more first build-up wiring layers (see figure 8); and a second resist layer (170) disposed on the lower surface of the third insulating layer (111b), the second resist layer covering at least a portion of the second wiring layer, wherein the first resist layer has a plurality of first openings exposing at least a portion of the uppermost first build-up wiring layer, and the second resist layer has a plurality of second openings exposing at least a portion of the second wiring layer (see figure 8 of Hwang).
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the printed circuit board of Naganuma to have bulid up layers and resist layers with wiring layers as taught by Hwang wherein Hwang mentions that the second passivation layer may protect the third built-up wiring layer from external physical and chemical damages and also works as solder resist, and may have a plurality of openings for exposing at least a portion of the built-up wiring layer for electrical connection to other devices and having build-up insulating layers so that accommodation of different wiring or circuit pattern layers and connection between the different wiring or circuit pattern layers through vias are possible as well as maintain electrical insulation to prevent any damage or short circuit between the different wiring or circuit pattern layers.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Naganuma and Goldberger et al. (US8004063, herein referred to as Goldberger).
Rejection of claim 16, Naganuma discloses the printed circuit board of claim 1, but fails to disclose further comprising: an inorganic insulating film covering at least a portion of each of the upper surface and the lower surface of the inorganic substrate, wherein the external surface of the inorganic substrate is spaced apart from the inorganic insulating film, and the external surface of the inorganic substrate is in contact with the first insulating layer.
Goldberger discloses a capacitor including a plurality of conductive trenches passing through a portion of the inorganic substrate from the upper surface or the lower surface of the inorganic substrate (see capacitor having 404 and 406 in figure 4 of Goldberger).
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the printed circuit board of Naganuma to have inorganic insulating film as taught by Chujo because embedding capacitors within the substrate eliminates the need for separate discrete components, freeing up valuable board area. This is especially important in high-density designs, mobile electronics, and compact electronics where component count and footprint are critical; and/or By placing capacitors close to the circuits they serve, printed embedded capacitors reduce parasitic inductance and resistance, improving impedance matching and/or reducing signal loss.
Allowable Subject Matter
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pertinent Prior Arts
The prior arts made of record and not relied upon is considered pertinent to applicant's disclosure. Please refer to the enclosed PTO-892 form for the citation of pertinent arts in the present case, all of which disclose various circuit boards.
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PARESH PAGHADAL whose telephone number is (571)272-5251. The examiner can normally be reached 7:00AM-4:00PM, Monday - Thursday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached on (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PARESH PAGHADAL/Primary Examiner, Art Unit 2847
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