DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Maalouf et al. (US 2023/0299720 A1) in view of Ji et al. (US 2023/0291359 A1).
Regarding claim 1:
Maalouf et al. discloses “a carrier amplifier configured to amplify a first radio frequency signal” (carrier amplifier 306 including carrier amplifier transistor 328, FIG. 3; ¶¶[0056], [0059]-[0060], [0063]).
Maalouf et al. further discloses “a peaking amplifier configured to amplify a second radio frequency signal” (peaking amplifier 308 including peaking amplifier transistor 348, FIG. 3; ¶¶[0056], [0064]-[0065], [0068]).
Maalouf et al. further discloses “a first bias circuit having a first bias control terminal to which a first bias control signal is input, a first bias output terminal configured to output a first bias current or a first bias voltage based on the first bias control signal to the carrier amplifier, and a first monitoring terminal configured to output a first monitoring signal representing a state of the first bias current or the first bias voltage” (FIGS. 2-3; ¶¶[0047]-[0050], [0053], [0063]). In particular, operational amplifier 220 outputs a DC bias voltage at node 232, which corresponds to the first bias control terminal receiving the first bias control signal. The DC bias voltage at node 232 is passed through inductor 248 of bias tee 238 to combining node 252 and is applied to gate terminal 106 of amplifier transistor 102, such that combining node 252 corresponds to the first bias output terminal. Source-voltage node 212, coupled to source terminal 210 of reference transistor 202, corresponds to the first monitoring terminal, wherein the source voltage VSOURCE varies with the threshold-voltage condition of reference transistor 202 and the corresponding amplifier transistor 102 and is used to generate the DC bias voltage. In the FIG. 3 Doherty embodiment, these elements correspond respectively to first inverter circuitry 324, first reference transistor 326, and carrier amplifier transistor 328 (¶[0063]).
Maalouf et al. further discloses “a second bias circuit having a second bias control terminal to which a second bias control signal is input, a second bias output terminal configured to output a second bias current or a second bias voltage based on the second bias control signal to the peaking amplifier, and a second monitoring terminal configured to output a second monitoring signal representing a state of the second bias current or the second bias voltage” (second reference transistor 346 together with second inverter circuitry 344, FIG. 3; ¶¶[0065], [0068]). Second inverter circuitry 344 outputs a DC bias voltage corresponding to the second bias control signal. The output of second inverter circuitry 344 corresponds to the second bias control terminal. The DC bias voltage is combined with the peaking input signal at a combining node coupled to the gate terminal of peaking amplifier transistor 348, which corresponds to the second bias output terminal. The source-voltage node at the source terminal of second reference transistor 346 corresponds to the second monitoring terminal, wherein the source voltage represents the threshold-voltage condition of second reference transistor 346 and corresponding peaking amplifier transistor 348 and is inverted by second inverter circuitry 344 to generate the DC bias voltage (FIG. 3; ¶¶[0065], [0067]-[0068]).
Maalouf et al. further discloses “a first differential amplifier having a first input terminal to which a constant voltage is input, a second input terminal electrically connected to the first monitoring terminal, and an output terminal electrically connected to the first bias control terminal, the first differential amplifier configured to output the first bias control signal based on a difference between the first monitoring signal and the constant voltage” (first inverter circuitry 324, which may employ inverter circuitry 204 of FIG. 2, including operational amplifier 220; ¶¶[0048], [0063]). Operational amplifier 220 includes non-inverting input 228 coupled to reference potential 120, corresponding to the first input terminal receiving the constant voltage. Inverting input 226 is coupled through first resistor 222 and node 230 to source-voltage node 212, corresponding to the second input terminal electrically connected to the first monitoring terminal. The output of operational amplifier 220 is provided at node 232, corresponding to the output terminal electrically connected to the first bias control terminal identified above. Operational amplifier 220 thereby generates the first bias control signal at node 232 based on the difference between the monitored source voltage and reference potential 120 (¶[0048]).
Maalouf et al. does not expressly disclose “a second differential amplifier having a first input terminal electrically connected to the first monitoring terminal and a second input terminal electrically connected to the second monitoring terminal, the second differential amplifier configured to output an amplified signal from an output terminal based on a difference between the second monitoring signal and the first monitoring signal.”
Ji et al. teaches a Doherty power amplifier having power adaptive biasing circuitry coupled between the carrier amplifier and the peaking amplifier and configured to sense a direct current base voltage of the carrier power transistor and, in response, adjust the bias of the peaking power transistor (Ji, claim 3). In FIG. 10, operational amplifier 136 has a non-inverting input coupled to first voltage V1 developed by the sense current drawn from carrier bias node 58 through sensing resistor RSENSE1 and diode-connected transistor DS1, and an inverting input coupled to second voltage V2 developed across resistor RE2 by the debias current drawn from peaking bias node 88 through isolation resistor RISO1 and sensor transistor QS1. The output of operational amplifier 136 is coupled to the base of sensor transistor QS1 at node 128 and thereby controls the current drawn from the peaking bias node. Operational amplifier 136 therefore receives a first signal representing the state of the carrier-side bias and a second signal representing the state of the peaking-side bias and outputs an amplified signal based on the difference between the two signals.
Maalouf et al. further discloses “an inverting amplifier configured to output the second bias control signal to the second bias control terminal, wherein the second bias control signal is based on inverting amplification of the amplified signal” (second inverter circuitry 344, FIG. 3; ¶¶[0065], [0068]). Second inverter circuitry 344 may employ inverter circuitry 204 of FIG. 2, including operational amplifier 220 configured as an operational-amplifier inverter (¶[0048]). In the combination with Ji et al., the amplified signal produced by the second differential amplifier is provided to second inverter circuitry 344, which performs the recited inverting amplification and provides the resulting second bias control signal for controlling the bias of peaking amplifier transistor 348.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Doherty amplifier system of Maalouf et al. to include a differential amplifier receiving the monitoring signal of the first bias circuit at one input and the monitoring signal of the second bias circuit at the other input, with the output of the differential amplifier supplied to the inverting amplifier that generates the peaking-amplifier bias control signal, as taught by Ji et al.
Ji et al. teaches adaptive biasing of the peaking amplifier based on the sensed state of the carrier amplifier in order to improve peaking-amplifier operation and load modulation. The modification would therefore constitute the use of a known technique to improve a similar device in the same way and would have yielded predictable results. One of ordinary skill in the art would have had a reasonable expectation of success because both Maalouf et al. and Ji et al. concern control of the carrier and peaking amplifier biases in a Doherty amplifier circuit.
Regarding claim 5:
Ji et al. further discloses sensor transistor QS1 having a base at node 128 coupled to the output of operational amplifier 136, a collector 130 coupled through isolation resistor RISO1 to peaking bias node 88, and an emitter 132 coupled through resistor RE2 to fixed voltage node G1 (FIG. 10; see also FIG. 3 and claim 4). Thus, Ji et al. teaches a transistor receiving the amplified signal at its base, having its collector electrically coupled to the peaking-amplifier bias control path, and having its emitter electrically coupled to a reference potential.
3. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Maalouf et al. (US 2023/0299720 A1) in view of Ji et al. (US 2023/0291359 A1), and further in view of Inagaki et al. (US 2004/0212423 A1).
Regarding claim 2:
Maalouf et al. in view of Ji et al. does not expressly disclose “wherein the inverting amplifier is a third differential amplifier having a first input terminal electrically connected to the output terminal of the second differential amplifier, a second input terminal electrically connected to a reference potential, and an output terminal electrically connected to the second bias control terminal.”
Inagaki et al. discloses first, second, and third differential amplifier circuits (FIG. 1; ¶¶[0023]-[0024]). Inagaki further discloses that differential amplifier circuit 3 is an amplifier circuit of inverting operation, wherein the (-) input side is connected to connection point N2 and the (+) input side is connected to bias line Va, which is a predetermined constant bias voltage (+VDD/2) (FIG. 1; ¶¶[0026]-[0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the inverting amplifier of Maalouf et al., as modified by Ji et al., to comprise a differential amplifier having one input receiving the signal to be inverted and another input receiving a constant reference potential, as taught by Inagaki et al., in order to provide differential amplification relative to a defined reference potential while providing an inverted amplified output.
4. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Maalouf et al. (US 2023/0299720 A1) in view of Ji et al. (US 2023/0291359 A1), and further in view of Marra et al. (US 2013/0127545 A1).
Regarding claim 3:
The combination of Maalouf et al. and Ji et al. discloses the limitations of claim 1 as set forth above, but does not expressly disclose “the second input terminal of the third differential amplifier is electrically connected to the second monitoring terminal.”
Marra et al. discloses a feedback loop including operational amplifier 464, wherein a non-inverting input of operational amplifier 464 receives a sensed voltage Vsense indicative of the DC voltage at the drain of NMOS transistor 412, and an inverting input is coupled to the drain of NMOS transistor 432 of replica circuit 430. Replica circuit 430 generates a reference voltage Vref for the feedback loop, with the voltage at the drain of NMOS transistor 432 being used as Vref (FIG. 6; ¶¶[0051]-[0052]). Operational amplifier 464 compares Vsense against Vref and generates Vbias1 such that Vsense matches Vref (¶¶[0052]-[0053]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the differential amplifier of Maalouf et al., as modified by Ji et al., to receive at its inputs respective monitored bias-condition signals, as taught by Marra et al., in order to provide feedback-based bias control responsive to monitored operating conditions and thereby compensate for variations in amplifier operating characteristics.
5. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Maalouf et al. (US 2023/0299720 A1) in view of Ji et al. (US 2023/0291359 A1) and Marra et al. (US 2013/0127545 A1), as applied to claim 3 above, and further in view of Thompson (US 6,731,173 B1).
Regarding claim 4:
Maalouf et al. in view of Ji et al. and Marra et al. disclose the limitations of claim 3 as set forth above, but does not expressly disclose “a potential level adjustment circuit electrically connected between the output terminal of the second differential amplifier and the first input terminal of the third differential amplifier, the potential level adjustment circuit configured to adjust a potential level of the amplified signal to a potential level of the second monitoring signal.”
Thompson discloses a scaling/level shifting circuit 238 configured to receive a voltage signal at node 132 and level shift or scale the voltage signal to produce a new voltage at node 248 (FIGS. 2–3). Thompson further discloses an embodiment in which Class C bias circuit 128 performs the level-shift and buffer functions and includes operational amplifier 402 and offset voltage source 404, wherein non-inverting input 406 is connected to node 132 and output 410 is connected to node 136. Operational amplifier 402 and offset voltage source 404 produce a buffered output voltage at node 136 equal to the voltage at node 132 minus the magnitude of the offset voltage (FIG. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the combination of Maalouf et al., Ji et al., and Marra et al. with the scaling/level shifting circuit taught by Thompson between the output of the second differential amplifier and the input of the third differential amplifier, in order to adjust the potential level of the amplified signal to a suitable potential level for subsequent differential amplification.
6. Claims 6, 7, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Maalouf et al. (US 2023/0299720 A1) in view of Ji et al. (US 2023/0291359 A1), and further in view of Okabe et al. (US 2019/0326865 A1) and Soga et al. (US 2021/0013842 A1).
Regarding claim 6:
The prior-art combination of Maalouf et al. and Ji et al. does not expressly disclose “the first bias circuit comprises a first output transistor configured to output the first bias current or the first bias voltage” and “a first negative feedback path from an emitter or a source of the first output transistor to a base or a gate of the first output transistor.”
Okabe et al. discloses an emitter-follower bias arrangement in which an emitter of transistor 84d is connected to the base of transistor 81a through resistor 84f. Okabe et al. further teaches that transistor 84d operates as an emitter-follower circuit whose emitter serves as an output, thereby teaching a first output transistor configured to output the first bias current or the first bias voltage (¶[0119]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first bias circuit of Maalouf et al. in view of Ji et al. to include the emitter-follower output transistor taught by Okabe et al. in order to provide the bias current or bias voltage to the amplifier transistor while maintaining a stable base potential, as taught by Okabe et al. Such a modification would have constituted the use of a known emitter-follower bias arrangement for its known and predictable bias-output function.
The combination of Maalouf et al., Ji et al., and Okabe et al. does not expressly disclose “a first negative feedback path from an emitter or a source of the first output transistor to a base or a gate of the first output transistor.”
Soga et al. discloses bias circuit 120 including output transistor 123. A power supply voltage Vcc is supplied to the collector of transistor 123, the base of transistor 123 is connected to the collector of transistor 121, and the emitter of transistor 123 supplies a bias current and bias voltage to amplifier transistor 110 (¶[0031]). The emitter of transistor 123 is further connected to the collector of transistor 124, and the collector and base of transistor 124 are connected through resistance element R2 (¶¶[0032], [0034]). When the emitter voltage of transistor 123 rises, the feedback arrangement causes the base voltage of transistor 123 to decrease, thereby decreasing the current through transistor 123 (¶[0038]). Soga et al. expressly identifies path X extending through transistors 124, 122, and 121 to the base of transistor 123 as providing negative feedback, thereby teaching the recited negative feedback path from the emitter of the output transistor to the base of the output transistor (¶[0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the bias circuit of Maalouf et al. in view of Ji et al. and Okabe et al. to include the negative-feedback arrangement taught by Soga et al. in order to prevent the emitter voltage of the output transistor from rising excessively and thereby provide a stable bias current or bias voltage. Soga et al. expressly teaches that its negative feedback path X produces this stabilization. The modification would therefore have been the use of a known negative feedback technique to improve a similar bias circuit in the same manner and would have yielded predictable results.
Regarding claim 7:
The prior-art combination of Maalouf et al. and Ji et al. does not expressly disclose “the second bias circuit comprises a second output transistor configured to output the second bias current or the second bias voltage and has a second negative feedback path from an emitter or a source of the second output transistor to a base or a gate of the second output transistor.”
Okabe et al. discloses that its second bias circuit 85 has substantially the same circuit configuration as its first bias circuit 84, except for an identified resistor difference (¶[0120]). As discussed with respect to the first bias circuit, the emitter-follower transistor operates with its emitter serving as the bias output (¶[0119]). Accordingly, Okabe et al. teaches providing the second bias circuit with a corresponding emitter-follower output transistor configured to output the second bias current or second bias voltage.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the second bias circuit of Maalouf et al. in view of Ji et al. to include the corresponding emitter-follower output transistor taught by Okabe et al., because Okabe expressly teaches using substantially the same bias-circuit configuration for its second bias circuit. The modification would provide the second bias current or voltage using the same known emitter-follower bias-output arrangement and would have yielded predictable results.
The combination of Maalouf et al., Ji et al., and Okabe et al. does not expressly disclose “a second negative feedback path from an emitter or a source of the second output transistor to a base or a gate of the second output transistor.”
Soga et al. discloses bias circuit 120 including output transistor 123, whose emitter supplies the bias current and bias voltage to amplifier transistor 110 (¶[0031]). When the emitter voltage of transistor 123 rises, Soga’s feedback circuitry causes the base voltage of transistor 123 to decrease, thereby decreasing the current through transistor 123 (¶[0038]). Soga expressly identifies path X extending through transistors 124, 122, and 121 to the base of transistor 123 as providing negative feedback and teaches that this feedback keeps the emitter voltage of transistor 123 from rising excessively so that a stable bias current and bias voltage are supplied (¶[0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the second bias circuit of Maalouf et al. in view of Ji et al. and Okabe et al. to include the negative-feedback arrangement taught by Soga et al. Because the second bias circuit likewise supplies a bias current or voltage to an amplifier transistor, applying Soga’s known negative-feedback arrangement to the second output transistor would prevent excessive variation in its output and thereby stabilize the second bias current or voltage. The modification therefore would have been the use of a known feedback technique for its known and predictable stabilizing function.
Regarding claim 12:
Claim 12 further requires that the inverting amplifier comprise “a transistor having a base or a gate to which the amplified signal is input, a collector or a drain electrically connected to the second bias control terminal, and an emitter or a source electrically connected to a reference potential,” and that “the first bias circuit comprises a first output transistor configured to output the first bias current or the first bias voltage, and has a first negative feedback path from an emitter or a source of the first output transistor to a base or a gate of the first output transistor.”
Ji et al. discloses the claimed transistor arrangement in FIG. 10. Sensor transistor QS1 has sensor base 128 connected to the output of operational amplifier 136, such that the amplified signal is supplied to the base of QS1. Sensor collector 130 is coupled through isolation resistor RISO1 to peaking bias node 88, and sensor emitter 132 is coupled through second emitter resistor RE2 to fixed voltage node G1. Accordingly, Ji et al. teaches a transistor having a base receiving the amplified signal, a collector electrically coupled to the second bias control terminal, and an emitter electrically coupled to a reference potential.
The combination of Maalouf et al. and Ji et al. does not expressly disclose that “the first bias circuit comprises a first output transistor configured to output the first bias current or the first bias voltage.”
Okabe et al. discloses an emitter-follower bias arrangement in which the emitter of transistor 84d is connected to the base of amplifier transistor 81a through resistor 84f. Okabe et al. expressly teaches that transistor 84d operates as an emitter-follower circuit whose emitter serves as an output, thereby teaching an output transistor configured to output the bias current or bias voltage (¶[0119]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first bias circuit of Maalouf et al. in view of Ji et al. to include the emitter-follower output transistor taught by Okabe et al. in order to provide the bias current or bias voltage to the amplifier transistor while maintaining a stable bias potential. Such a modification would have constituted the use of a known emitter-follower bias arrangement for its known and predictable bias-output function.
The combination of Maalouf et al., Ji et al., and Okabe et al. does not expressly disclose “a first negative feedback path from an emitter or a source of the first output transistor to a base or a gate of the first output transistor.”
Soga et al. discloses bias circuit 120 including output transistor 123, whose emitter supplies a bias current and bias voltage to amplifier transistor 110 (¶[0031]). When the emitter voltage of transistor 123 increases, the feedback circuitry causes the base voltage of transistor 123 to decrease, thereby decreasing current through transistor 123 (¶[0038]). Soga et al. further expressly identifies path X extending through transistors 124, 122, and 121 to the base of transistor 123 as providing negative feedback. Path X thereby provides the recited negative feedback path from the emitter side of output transistor 123 back to the base of output transistor 123 and stabilizes the supplied bias current and bias voltage (¶[0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the bias circuit of Maalouf et al. in view of Ji et al. and Okabe et al. to include the negative-feedback arrangement taught by Soga et al. in order to prevent excessive variation in the output-transistor voltage and thereby provide a stable bias current or bias voltage. Soga et al. expressly teaches that its negative feedback path provides this stabilizing function. The modification therefore would have constituted the use of a known negative feedback technique to improve a similar bias circuit in the same manner and would have yielded predictable results.
7. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Maalouf et al. (US 2023/0299720 A1) in view of Ji et al. (US 2023/0291359 A1), and further in view of Inagaki et al. (US 2004/0212423 A1), as applied to claim 2 above, and further in view of Okabe et al. (US 2019/0326865 A1) and Soga et al. (US 2021/0013842 A1).
Regarding claim 9:
Claim 9 further requires that the inverting amplifier is “a third differential amplifier having a first input terminal electrically connected to the output terminal of the second differential amplifier, a second input terminal electrically connected to a reference potential, and an output terminal electrically connected to the second bias control terminal,” and that “the first bias circuit comprises a first output transistor configured to output the first bias current or the first bias voltage, and has a first negative feedback path from an emitter or a source of the first output transistor to a base or a gate of the first output transistor.”
Maalouf et al. discloses second inverter circuitry 344, which may employ inverter circuitry 204 of FIG. 2 including operational amplifier 220. Operational amplifier 220 includes non-inverting input 228 coupled to reference potential 120, and its output provides the DC bias voltage used to bias peaking amplifier transistor 348 (¶¶[0048], [0068]).
Inagaki et al. further teaches the use of a differential amplifier as an inverting amplifier stage. In FIG. 1, differential amplifier circuit 3 operates as an inverting amplifier having its inverting input connected to node N2 and its non-inverting input connected to bias line Va, which provides a reference potential. Inagaki further teaches that node N2 receives the signal supplied through resistor R3 from the output of a preceding differential amplifier stage (¶¶[0026]-[0027]). Thus, Inagaki teaches an inverting differential-amplifier stage receiving the output signal of a preceding differential amplifier at one input and a reference potential at the other input.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the inverting amplifier of Maalouf et al. in view of Ji et al. as a third differential amplifier in accordance with Inagaki et al., with the amplified signal output by the second differential amplifier supplied to one input and a reference potential supplied to the other input, and with the output providing the second bias control signal. Inagaki teaches the use of such an inverting differential-amplifier configuration for processing the output of a preceding differential-amplifier stage relative to a reference potential, and the modification would have amounted to using a known differential-amplifier implementation for its known and predictable inverting function.
The combination of Maalouf et al., Ji et al., and Inagaki et al. does not expressly disclose that “the first bias circuit comprises a first output transistor configured to output the first bias current or the first bias voltage.”
Okabe et al. discloses an emitter-follower bias arrangement in which the emitter of transistor 84d is connected to the base of amplifier transistor 81a through resistor 84f. Okabe et al. teaches that transistor 84d operates as an emitter-follower circuit whose emitter serves as an output, thereby teaching a first output transistor configured to output the first bias current or the first bias voltage (¶[0119]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the first bias circuit of Maalouf et al. in view of Ji et al. and Inagaki et al. to include the emitter-follower output transistor taught by Okabe et al. in order to provide the bias current or bias voltage to the amplifier transistor while maintaining a stable bias potential. Such a modification would have constituted the use of a known emitter-follower bias arrangement for its known and predictable bias-output function.
The combination of Maalouf et al., Ji et al., Inagaki et al., and Okabe et al. does not expressly disclose “a first negative feedback path from an emitter or a source of the first output transistor to a base or a gate of the first output transistor.”
Soga et al. discloses bias circuit 120 including output transistor 123, whose emitter supplies a bias current and bias voltage to amplifier transistor 110 (¶[0031]). When the emitter voltage of transistor 123 increases, the feedback circuitry causes the base voltage of transistor 123 to decrease, thereby decreasing current through transistor 123 (¶[0038]). Soga et al. expressly identifies path X extending through transistors 124, 122, and 121 to the base of transistor 123 as providing negative feedback. Path X thereby provides the recited negative feedback path from the emitter side of output transistor 123 back to the base of output transistor 123 and stabilizes the supplied bias current and bias voltage (¶[0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the bias circuit of Maalouf et al. in view of Ji et al., Inagaki et al., and Okabe et al. to include the negative feedback arrangement taught by Soga et al. in order to prevent excessive variation in the output transistor voltage and thereby provide a stable bias current or bias voltage. Soga et al. expressly teaches that its negative feedback path provides this stabilizing function. The modification therefore would have constituted the use of a known negative feedback technique to improve a similar bias circuit in the same manner and would have yielded predictable results.
8. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Maalouf et al. (US 2023/0299720 A1) in view of Ji et al. (US 2023/0291359 A1) and Marra et al. (US 2013/0127545 A1), as applied to claim 3 above, and further in view of Okabe et al. (US 2019/0326865 A1) and Soga et al. (US 2021/0013842 A1).
Regarding claim 10:
Claim 10 further requires that the inverting amplifier is “a third differential amplifier having a first input terminal electrically connected to the output terminal of the second differential amplifier, a second input terminal electrically connected to the second monitoring terminal, and an output terminal electrically connected to the second bias control terminal,” and that “the first bias circuit comprises a first output transistor configured to output the first bias current or the first bias voltage, and has a first negative feedback path from an emitter or a source of the first output transistor to a base or a gate of the first output transistor.”
Maalouf et al. discloses second inverter circuitry 344, which may employ inverter circuitry 204 of FIG. 2 including operational amplifier 220, with an input receiving the signal to be inverted and an output providing the DC bias voltage used to bias peaking amplifier transistor 348 (¶¶[0048], [0068]). In the combination with Ji et al., the first input of the operational amplifier receives the amplified signal output by the second differential amplifier.
Marra et al. further teaches a differential amplifier feedback arrangement in which operational amplifier 464 receives a sensed voltage, Vsense, at one input and a reference voltage, Vref, generated by a replica sensing branch at the other input. Operational amplifier 464 compares Vsense with Vref and generates bias voltage Vbias1 based on the difference between those signals (FIG. 6; ¶¶[0051]-[0053]). Thus, Marra teaches that the two inputs of a bias-generating differential amplifier may receive respective bias-state-related monitoring signals rather than requiring one input to remain connected to a fixed reference potential.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the peaking-side differential amplifier of Maalouf et al., as modified by Ji et al., so that its second input is connected to the second monitoring terminal as taught by Marra et al., in order to regulate the peaking amplifier bias based on the monitored bias state and compensate for variations affecting the amplifier bias. Such modification would have constituted the use of a known feedback technique to improve a similar bias-control circuit in the same manner and would have yielded predictable results.
The combination of Maalouf et al., Ji et al., and Marra et al. does not expressly disclose that “the first bias circuit comprises a first output transistor configured to output the first bias current or the first bias voltage.”
Okabe et al. discloses an emitter-follower bias arrangement in which an emitter of transistor 84d is connected to the base of amplifier transistor 81a through resistor 84f. Okabe et al. teaches that transistor 84d operates as an emitter follower circuit whose emitter serves as an output, thereby teaching a first output transistor configured to output the first bias current or the first bias voltage (¶[0119]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the first bias circuit of Maalouf et al. in view of Ji et al. and Marra et al. to include the emitter-follower output transistor taught by Okabe et al. in order to provide the bias current or bias voltage to the amplifier transistor while maintaining a stable bias potential. Such modification would have constituted the use of a known emitter-follower bias arrangement for its known and predictable bias-output function.
The combination of Maalouf et al., Ji et al., Marra et al., and Okabe et al. does not expressly disclose “a first negative feedback path from an emitter or a source of the first output transistor to a base or a gate of the first output transistor.”
Soga et al. discloses bias circuit 120 including output transistor 123, whose emitter supplies a bias current and bias voltage to amplifier transistor 110 (¶[0031]). When the emitter voltage of transistor 123 rises, the feedback circuitry causes the base voltage of transistor 123 to decrease, thereby decreasing the current through transistor 123 (¶[0038]). Soga et al. further identifies path X extending through transistors 124, 122, and 121 to the base of transistor 123 as providing negative feedback. Path X thereby provides the recited negative-feedback path from the emitter side of output transistor 123 back to the base of output transistor 123 and stabilizes the supplied bias current and bias voltage (¶[0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the bias circuit of Maalouf et al. in view of Ji et al., Marra et al., and Okabe et al. to include the negative-feedback arrangement taught by Soga et al. in order to prevent excessive variation in the output-transistor voltage and thereby provide a stable bias current or bias voltage. Soga et al. expressly teaches that its negative feedback path provides this stabilizing function. The modification therefore would have constituted the use of a known negative feedback technique to improve a similar bias circuit in the same manner and would have yielded predictable results.
9. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Maalouf et al. (US 2023/0299720 A1) in view of Ji et al. (US 2023/0291359 A1), Marra et al. (US 2013/0127545 A1), and Thompson (US 6,731,173 B1), as applied to claim 4 above, and further in view of Okabe et al. (US 2019/0326865 A1) and Soga et al. (US 2021/0013842 A1).
Regarding claim 11:
Claim 11 further requires that the circuit comprises “a potential level adjustment circuit that is electrically connected between the output terminal of the second differential amplifier and the first input terminal of the third differential amplifier, and that is configured to adjust a potential level of the amplified signal to a potential level of the second monitoring signal,” and that “the first bias circuit comprises a first output transistor configured to output the first bias current or the first bias voltage, and has a first negative feedback path from an emitter or a source of the first output transistor to a base or a gate of the first output transistor.”
Thompson et al. discloses, in a Doherty bias circuit, a scaling/level-shifting circuit 238 interposed between a current mirror circuit coupled to the carrier amplifier and a voltage buffer coupled to the peaking amplifier. Thompson further discloses an embodiment in which an operational amplifier 402 and offset voltage source 404 operate to produce a buffered output voltage at node 136 equal to the voltage at node 132 minus the magnitude of the offset voltage source 404. Thompson therefore teaches adjusting the potential level of an input signal before the signal is supplied to a subsequent amplifier stage.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Maalouf et al. in view of Ji et al. and Marra et al. by electrically connecting Thompson’s level-adjustment circuitry between the output terminal of the second differential amplifier and the first input terminal of the third differential amplifier, in order to adjust the potential level of the amplified signal to a level suitable for comparison with the second monitoring signal. Thompson expressly teaches scaling or shifting a carrier-derived signal before supplying it to the circuitry controlling the peaking amplifier. The modification therefore would have constituted the use of a known level-shifting technique for its known and predictable function.
The combination of Maalouf et al., Ji et al., Marra et al., and Thompson et al. does not expressly disclose that “the first bias circuit comprises a first output transistor configured to output the first bias current or the first bias voltage.”
Okabe et al. discloses an emitter-follower bias arrangement in which an emitter of transistor 84d is connected to the base of amplifier transistor 81a through resistor 84f. Okabe et al. teaches that transistor 84d operates as an emitter-follower circuit whose emitter serves as an output, thereby teaching a first output transistor configured to output the first bias current or the first bias voltage (¶[0119]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the first bias circuit of Maalouf et al. in view of Ji et al., Marra et al., and Thompson et al. to include the emitter-follower output transistor taught by Okabe et al. in order to provide the bias current or bias voltage to the amplifier transistor while maintaining a stable bias potential. Such modification would have constituted the use of a known emitter-follower bias arrangement for its known and predictable bias-output function.
The combination of Maalouf et al., Ji et al., Marra et al., Thompson et al., and Okabe et al. does not expressly disclose “a first negative feedback path from an emitter or a source of the first output transistor to a base or a gate of the first output transistor.”
Soga et al. discloses bias circuit 120 including output transistor 123, whose emitter supplies a bias current and bias voltage to amplifier transistor 110 (¶[0031]). When the emitter voltage of transistor 123 rises, the feedback circuitry causes the base voltage of transistor 123 to decrease, thereby decreasing the current through transistor 123 (¶[0038]). Soga et al. further identifies path X extending through transistors 124, 122, and 121 to the base of transistor 123 as providing negative feedback. Path X thereby provides the recited negative-feedback path from the emitter side of output transistor 123 back to the base of output transistor 123 and stabilizes the supplied bias current and bias voltage (¶[0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the bias circuit of Maalouf et al. in view of Ji et al., Marra et al., Thompson et al., and Okabe et al. to include the negative-feedback arrangement taught by Soga et al. in order to prevent excessive variation in the output-transistor voltage and thereby provide a stable bias current or bias voltage. Soga et al. expressly teaches that its negative feedback path provides this stabilizing function. The modification therefore would have constituted the use of a known negative feedback technique to improve a similar bias circuit in the same manner and would have yielded predictable results.
10. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Maalouf et al. in view of Ji et al., Okabe et al., and Soga et al., as applied to claim 6 above, and further in view of Hase et al. (US 10,326,481 B2).
Regarding claim 8:
The prior-art combination above does not expressly disclose “the second bias circuit comprises a second output transistor configured to output the second bias current or the second bias voltage, the second output transistor having a base or a gate electrically connected to the base or the gate of the first output transistor.”
Ji et al. discloses a carrier power bias generator 78 coupled to the carrier amplifier and a peaking power bias generator 112 coupled to the peaking amplifier, thereby teaching respective carrier-side and peaking-side bias circuitry. Ji et al. further discloses, in FIG. 8, power adaptive biasing circuitry 20 including current mirror 134 having reference transistor QREF1 and mirror transistor QMIR1. The bases of QREF1 and QMIR1 are electrically connected to form the current mirror. Ji et al. explains that current mirror 134 permits control of the relationship between the sensed current Isense and the debias current Idebias by selection of the emitter-area ratio M (¶[0056]).
Hase et al. further discloses a power amplification module including first bias circuit 210 and second bias circuit 211. First bias circuit 210A includes output transistor 312A, whose emitter outputs bias current IBIAS1 to amplification transistor 300A. Hase further teaches that second bias circuit 211 supplies bias current IBIAS2 to the second-stage amplification circuit 201 and may have the same configuration as first bias circuit 210A. Accordingly, when the same configuration is employed, second bias circuit 211 includes a corresponding second output transistor configured to output the second bias current or second bias voltage.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first and second bias circuits of the combination to employ the corresponding output-transistor arrangement taught by Hase et al. Hase expressly teaches using substantially the same bias-circuit configuration for the second amplification stage as for the first amplification stage, thereby providing a known and predictable arrangement for supplying respective bias currents to the two amplifier stages.
It would further have been obvious to electrically connect the bases of the first and second output transistors in accordance with the current-mirror technique taught by Ji et al. Ji demonstrates that electrically connecting the bases of corresponding transistors in a current-mirror arrangement permits the currents in the respective branches to track according to a predetermined scaling relationship. Applying that known common-base current-mirror arrangement to Hase’s corresponding first and second bias-output transistors would cause their bias outputs to track in a predictable manner and would constitute the use of a known current-mirror technique for its known current-tracking function.
Conclusion
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/S.S./Examiner, Art Unit 2843
/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
