DETAILED ACTION
This office action is in response to the remarks filed on 07/23/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8-11 and 13-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kinder US 20150349762.
Regarding Claim 1, Kinder teaches (Figures 1-7) a circuit (100), comprising: a switching circuit (110-120) including a high side switch connected to a low side switch (110 and 120) at a switch node (phase node); a controller (producing IN, 130 and 220) arranged to generate a high side control signal and a low side control signal (GHS and GLS signals); a high side variable delay circuit (top circuitry of 230-250 and And1-2, see fig. 2) arranged to receive the high side control signal (and1-2 inputs) and in response, transmit a corresponding delayed high side control signal (from 250, counter 1); a low side variable delay circuit (bottom circuitry of 230-250 and And3-4, see fig. 2) arranged to receive the low side control signal (inputs of and3-4) and in response, transmit a corresponding delayed low side control signal; (from 250 counter 2); a high side driver circuit (at Fig. 6a) arranged to transmit a high side drive signal (HS gate) to the high side switch (110) in response to receiving the delayed high side control signal (Delay HS); and a low side driver circuit (Fig. 6b) arranged to transmit a low side drive signal (Ls gate) to the low side switch (120) in response to receiving the delayed low side control signal (Delay LS); and wherein the low side variable delay circuit (bottom circuitry of 230-250 and And3-4) is arranged to change a low side delay time (with 240-250 bottom circuitry ) such that a rising edge of an output signal of the low side driver circuit (LS fate) occurs after a voltage at the switch node goes to zero (during deadtime when 110 and 120 are in the off state, par. 18 and 21-22). (For example: Par. 17-22, 35-39 and 47-52)
Regarding Claims 2 and 15, Kinder teaches (Figures 1-7)wherein the controller (130 and 220) is further arranged to generate a particular high side control signal (with 220 GHS signal), and wherein the High side variable delay circuit (top circuitry of 230-250 and And1-2) is arranged to change a high side delay time based on a sign of a timing difference (with latch SR1 and 241) between a first signal (at terminal A) corresponding with the particular high side control signal and a second signal (at terminal B) corresponding with the low side drive signal (LS). (For example: Par. 17-22, 35-39 and 47-52)
Regarding Claims 3 and 16, Kinder teaches (Figures 1-7) wherein the high side delay time is increased (when the SR latch is set) in response to the first signal occurring before the second signal (par. 47-51). (For example: Par. 17-22, 35-39 and 47-52)
Regarding Claims 4 and 17, Kinder teaches (Figures 1-7) wherein the high side delay time is decreased (when the SR latch is reset) in response to the first signal occurring after the second signal (par. 47-51). (For example: Par. 17-22, 35-39 and 47-52)
Regarding Claims 5 and 18, Kinder teaches (Figures 1-7)wherein the high side variable delay circuit (top circuitry of 230-250 and And1-2) is arranged to cease changing the high side delay time in response to a plurality of signs of timing differences between pairs of first and second signals (counting operation of counter 1) having occurred in a predetermined sequential pattern (par. 53-54). (For example: Par. 17-22, 35-39 and 47-52)
Regarding Claim 8, Kinder teaches (Figures 1-7) wherein the low side variable delay circuit (bottom circuitry of 230-250 and And3-4) is arranged to change a low side delay time (delay time for 120) based on a sign of a timing difference (done with SR2 and 242) between a first signal corresponding with a low side drive signal and a second signal corresponding with the high side drive signal (signals at terminals C and D which are generated based on GHS and GLS signals). (For example: Par. 17-22, 35-39 and 47-52)
Regarding Claim 9, Kinder teaches (Figures 1-7) wherein the low side delay time (Delay time for 120) is increased (when SR2 is Set)in response to the first signal occurring before the second signal (par. 47-52). (For example: Par. 17-22, 35-39 and 47-52)
Regarding Claim 10, Kinder teaches (Figures 1-7), wherein the low side delay time (delay time for 120) is decreased (when SR2 is reset) in response to the first signal occurring after the second signal (par. 47-52). (For example: Par. 17-22, 35-39 and 47-52)
Regarding Claim 11, Kinder teaches (Figures 1-7) wherein the low side variable delay circuit (bottom circuitry of 230-250 and And3-4) is arranged to cease changing the low side delay time (delay for 120) in response to a plurality of signs of timing differences between pairs of first and second signals (done with 240) having occurred in a predetermined sequential pattern (at 250, par. 52-54). (For example: Par. 17-22, 35-39 and 47-52)
Regarding Claim 13, Kinder teaches (Figures 1-7) a method comprising: providing a switching circuit (100) including a high side switch (110) connected to a low side switch (120) at a switch node (phase node); providing a high side driver circuit (Fig. 6a) coupled to the high side switch (110) and a low side driver circuit (Fig. 6b) coupled to the low side switch (120), generating by a controller (circuit producing IN and 220) a plurality of high side control signals and a plurality of low side control signals (GHS and GLS signal with 220); generating by a high side variable delay circuit (top circuitry of 230-250 and And1-2) a corresponding delayed high side control signal (HS delay) in response to receiving each of the plurality of high side control signals (inputs to And gates 1-2); generating, by a low side variable delay circuit (bottom circuitry of 230-250 and And3-4) a corresponding delayed low side control signal (LS delay) in response to receiving each of the plurality of low side control signals (input to and gates 3-4); electrically connecting the switch node to a power supply (Vdd) via the high side switch (110) in response to receiving the delayed high side control signal (HS delay, turn on 110); and electrically connecting the switch node to a ground node (Vss) via the low side switch (120) in response to receiving the delayed low side control signal (LS delay). (For example: Par. 17-22, 35-39 and 47-52)
Regarding Claim 14, Kinder teaches (Figures 1-7)wherein after electrically connecting the switch node (phase node) to the power supply (Vdd), the delayed high side control signal (HS delay) causes the high side switch to disconnect the switch node from the power supply (when turning of the switch 110). (For example: Par. 17-22, 35-39 and 47-52)
Regarding Claim 19, Kinder teaches (Figures 1-7)wherein after electrically connecting the switch node (phase node) to the ground node (Vss), the delayed low side control signal (LS Delay) causes the low side switch to disconnect the switch node from the ground node (turning off the switch 120). (For example: Par. 17-22, 35-39 and 47-52)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kinder US 20150349762 in view of Barrenscheen et al US 2014/0002141.
Regarding Claims 6 and 12, Kinder teaches (Figures 1-7) the circuit.
Kinder does not teach a shift register arranged to store data representing the plurality of signs of the timing differences; and a comparator arranged to compare a stored data of the shift register to data representing the predetermined sequential pattern.
Barrenscheen teaches (Figures 6-9) a shift register (at 548, par. 44) arranged to store data representing the plurality of signs of the timing differences (counter counts the timing done by 542 ); and a comparator (at 542 which does the comparison between the Cout and the stored TLTO, par. 45) arranged to compare a stored data of the shift register to data representing the predetermined sequential pattern (count). (For example: Par. 43-46)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Kinder to include a shift register arranged to store data representing the plurality of signs of the timing differences; and a comparator arranged to compare a stored data of the shift register to data representing the predetermined sequential pattern, as taught by Barrenscheen to allow the controller to run cooler and be more stable by eliminating the high peak currents.
Claim(s) 7 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kinder US 20150349762 in view of Bridge US 6396250.
Regarding Claims 7 and 20, Kinder teaches (Figures 1-7) the circuit.
Kinder does not teach wherein the high side delay time is programmable.
Bridge teaches (Figure 7)wherein the high side delay time (at 722) is programmable (see fig. 7). (For example: Col. 7)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Kinder to include wherein the high side delay time is programmable, as taught by Bridge to allow for different values of deadtimes to be stored and used for improvement of efficiency of the system.
Response to Arguments
Applicant's arguments filed 07/23/2026 have been fully considered but they are not persuasive.
Applicant argued that “Kinder does not monitor, sense, or respond to a voltage at the switch node (output node OUT)”.In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., monitor, sense, or respond to a voltage at the switch node) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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