DETAILED ACTION
The present Office Action is in response to Applicant Arguments/Remarks and amended claims filed on 02/02/2026. Claims 1, 7, 11, and 20 have been amended. Claims 1-20 remain pending in the application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application, 17/684,129 filed on 03/01/2022, under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Response to Amendments and Arguments
Applicant’s amendments and remarks have been fully considered, with the Examiner’s response set forth below.
(1)In view of Applicant’s remarks regarding the double patenting rejection in that Applicant requests that this rejection be held in abeyance, the double patenting rejection has been maintained in the present Office Action as a reminder for Applicant to timely file a terminal disclaimer
(2) Applicant’s arguments are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
(3) Another iteration of claim analysis has been made. Refer to the corresponding sections of the claim analysis below for details.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “transmitting a signal to read parity data stored in the memory device, wherein the signal to read the parity data is transmitted to the memory device in the absence of transmitting a signal associated with a read operation to read data corresponding to the parity data stored in the memory device”. The limitation “the signal to read the parity data is transmitted to the memory device in the absence of transmitting a signal associated with a read operation to read data corresponding to the parity data stored in the memory device” can be interpreted multiple ways:1) a signal associated with a read operation to read data corresponding to the parity data stored in the memory device is never transmitted and 2) a signal associated with a read operation to read data corresponding to the parity data stored in the memory device is transmitted independently from the signal to read parity data stored in the memory device (i.e. as long as the two signals are not transmitted at the same time). For examination purpose, the Examiner has interpreted the limitation as 1) a signal associated with a read operation to read data corresponding to the parity data stored in the memory device is never transmitted. Claims 7 and 11 recite similar limitations and they are rejected for the same reason. Claims 2-6, 8-10, and 12-20 are depending on claims 1, 7, and 11 respectively and the dependent claims are rejected for the same reason as they do not cure the deficiencies set forth above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-6, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2022/0317920), hereinafter Park in view of Agombar et al. (US2018/0095824), hereinafter Agombar, and further in view of Kim (US2023/0063280), hereinafter Kim.
Regarding claim 1, Park teaches an apparatus, comprising:
a memory device (Park, [0029], two or more memory devices may be included in the memory system 1000; Fig.1); and
a controller coupled the memory device and comprising a cache (Park, [0031], The controller 1200 may include a cache), wherein the controller is configured to:
receive a memory access request (Park, [0054], the host interface 510 may receive a program request; [0074]);
cache data corresponding to the memory access request in a first location in the cache (Park, [0064], first cache); cache the data corresponding to the memory access request in a second location in the cache (Park, [0063], the cache group 420 may include at least three caches 1CAH, 2CAH, and 3CAH; [0064], during the program operation, first data 1DATA may be data output from the host 2000, and may be temporarily stored in the first cache 1CAH and then transmitted to the third cache 3CAH);
receive a further memory access request (Park, [0005], a controller configured to in response to a program request or a read request for a selected memory block among the memory blocks being received from a host); and
perform a cache write-back operation in response to receiving the further memory access request by:
transmitting a signal associated with a read operation to read cached data at the second location; and
transmitting a signal to read parity data stored in the memory device, wherein the signal to read the parity data is transmitted to the memory device in the absence of transmitting a signal associated with a read operation to read data corresponding to the parity data stored in the memory device.
Park does not explicitly teach perform a cache write-back operation in response to receiving the further memory access request by: transmitting a signal associated with a read operation to read cached data at the second location; and transmitting a signal to read parity data stored in the memory device, wherein the signal to read the parity data is transmitted to the memory device in the absence of transmitting a signal associated with a read operation to read data corresponding to the parity data stored in the memory device, as claimed.
However, Park in view of Agombar teaches receive a further memory access request (Agombar, [0006], receiving a write request comprising new data for overwriting corresponding old data in cache)
perform a cache write-back operation (Agombar, [0034], When the new data 300 b is destaged) in response to receiving the further memory access request by:
transmitting a signal associated with a read operation to read cached data at the second location (Agombar, [0006], performs an XOR (exclusive OR) operation on the new data and the old data to yield a parity delta; [0034], Because this data 300 a resides in cache 216, if and when the data 300 a is overwritten, parity delta information 302 b may be readily calculated using the old data 300 a and the new incoming data 300 b prior to overwriting the old data 300 a; Note – old data in the cache needs to be read in order to perform an XOR operation); and
transmitting a signal to read parity data stored in the memory device (Agombar, [0036], when the new data 300 b is destaged to the RAID layer 306 so that it can be written to the RAID 310 … apply the parity delta 400 to a parity value in the stride 600; [0037], In this example … The RAID layer 306 further applies the parity delta 400 received from the cache 216 to the parity value 602 in the stride 600. This may be accomplished by XORing the parity delta 400 with the parity value 602.), wherein the signal to read the parity data is transmitted to the memory device in the absence of transmitting a signal associated with a read operation to read data corresponding to the parity data stored in the memory device (Agombar, [0034], when data is destaged from a cache 216 to a RAID 310, a copy of the data often remains in the cache 216 in the event it is needed again. Because this data 300 a resides in cache 216, if and when the data 300 a is overwritten, parity delta information 302 b may be readily calculated using the old data 300 a and the new incoming data 300 b prior to overwriting the old data 300 a … When the new data 300 b is destaged, the new data 300 b may be written to the RAID 310 and the parity delta 302 b may be applied to (e.g., XORed with) the parity value of the stride containing the new data 300 b. This will reduce or eliminate the need to read data from the RAID 310 to calculate the new parity value).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Park to incorporate teachings of Agombar to generate a parity delta value by using old user data stored in a cache instead of reading the old user data from a storage device during a cache de-staging operation. A person of ordinary skill in the art would have been motivated to combine the teachings of Park with Agombar because it improves efficiency and performance of the storage system disclosed in Park by eliminating a read operation for retrieving old data from a storage device during a cache de-staging operation, which reduces I/O latency for the storage system.
The combination of Park teaches writing back data from a cache to a storage device, nevertheless, the combination of Park does not explicitly teach perform a cache write-back operation in response to receiving the further memory access request.
However, the combination of Park in view of Kim teaches perform a cache write-back operation in response to receiving the further memory access request (Kim, [0203], when the command pattern is a write pattern, flushing all or part of the data stored in a write buffer WR_BUF, which stores data write-requested by the host HOST, into the memory device 110 in order to process the write command received from the host HOST).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Park to incorporate teachings of Kim to include a flush command from a host to instruct a controller to perform a flush operation. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Park with Kim because it improves efficiency and communication of the storage system disclosed in the combination of Park by allowing a host to issue commands to control I/O memory accesses in a storage device.
Regarding claim 2, the combination of Park teaches all the features with respect to claim 1 as outlined above. The combination of Park further teaches the apparatus of claim 1, wherein the memory access request is received from a host (Park, [0029], the memory system 1000 may be configured to store, erase, or output data in response to a request of a host 2000; [0030]).
Regarding claim 4, the combination of Park teaches all the features with respect to claim 1 as outlined above. The combination of Park further teaches the apparatus of claim 1, wherein the data cached in the first location in the cache is an identical copy of the data cached in the second location in the cache (Park, [0074], The controller 1200 may transmit the data temporarily stored in the first cache 1CAH to a third cache 3CAH at S93).
Regarding claim 5, the combination of Park teaches all the features with respect to claim 1 as outlined above. The combination of Park further teaches the apparatus of claim 1, further comprising: perform an operation to determine updated parity data based on: the parity data; the cached data read from the second location in the cache; and data associated with the further memory access request (Agombar, [0034], if and when the data 300 a is overwritten, parity delta information 302 b may be readily calculated using the old data 300 a and the new incoming data 300 b prior to overwriting the old data 300 a. The parity delta 302 b may be stored in cache 216 along with the new data 300 b, and destaged from the cache 216 along with the new data 300 b. When the new data 300 b is destaged, the new data 300 b may be written to the RAID 310 and the parity delta 302 b may be applied to (e.g., XORed with) the parity value of the stride containing the new data 300 b).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Park to incorporate teachings of Agombar to generate a parity data for a new user data by using old user data, new user data, parity delta value and old parity data. A person of ordinary skill in the art would have been motivated to combine the teachings of Park with Agombar because it improves efficiency and performance of the storage system disclosed in Park by eliminating a read operation for retrieving old data from a storage device during a cache de-staging operation, which reduces I/O latency for the storage system.
Regarding claim 6, the combination of Park teaches all the features with respect to claim 5 as outlined above. The combination of Park further teaches the apparatus of claim 5, further comprising: transmit a signal to store the updated parity data in the memory device (Agombar, [0037], This may be accomplished by XORing the parity delta 400 with the parity value 602. This updates the parity value 602 to reflect the newly written data 300 b in the stride 600.); and transmit a signal to store the data associated with the further memory access request in the memory device (Agombar, [0036], The RAID layer 306 may write the new data 300 b to the RAID 310; Park, [0054]; Kim, [0203]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Park to incorporate teachings of Agombar to transmit signals to store new user data and updated parity data in a storage device. A person of ordinary skill in the art would have been motivated to combine the teachings of Park with Agombar because it improves efficiency and performance of the storage system disclosed in Park by eliminating a read operation for retrieving old data from a storage device during a cache de-staging operation, which reduces I/O latency for the storage system.
Regarding claim 11, Park teaches an apparatus, comprising:
a number of memory devices (Park, [0029], two or more memory devices may be included in the memory system 1000; Fig.1); and
a controller coupled to the number of memory devices (Park, Fig. 1, controller 1200), wherein the controller includes a cache (Park, [0031], The controller 1200 may include a cache) and is configured to:
receive a memory access request to access data (Park, [0031], the controller 1200 may temporarily store data in the cache. After that, when a read request for reading the data stored in the cache is input thereto; [0074]); and
perform one or more memory operations corresponding to the memory access request to access the cache or one or more of the number of memory devices, or both (Park, [0031], The controller 1200 may include a cache in order to quickly perform the read operation corresponding to the request of the host 2000 or an internal request of the memory system 1000), including performance of memory operations to:
store the data in a first location in the cache (Park, [0064], first cache);
store the data in a second location in the cache (Park, [0063], the cache group 420 may include at least three caches 1CAH, 2CAH, and 3CAH; [0064], during the program operation, first data 1DATA may be data output from the host 2000, and may be temporarily stored in the first cache 1CAH and then transmitted to the third cache 3CAH);
receive a further memory access request (Park, [0005], a controller configured to in response to a program request or a read request for a selected memory block among the memory blocks being received from a host); and
perform a cache write-back operation in response to receiving the further memory access request, wherein the controller is further configured to:
read cached data at the second location; and
read parity data stored in the one or more of the number of memory devices, wherein the parity data is read from the memory device in the absence of reading data corresponding to the parity data stored in the one or more of the number of memory devices.
Park does not explicitly teach perform a cache write-back operation in response to receiving the further memory access request, wherein the controller is further configured to: read cached data at the second location; and read parity data stored in the one or more of the number of memory devices, wherein the parity data is read from the memory device in the absence of reading data corresponding to the parity data stored in the one or more of the number of memory devices, as claimed.
However, Park in view of Agombar teaches receive a further memory access request (Agombar, [0006], receiving a write request comprising new data for overwriting corresponding old data in cache); and
perform a cache write-back operation (Agombar, [0034], When the new data 300 b is destaged) in response to receiving the further memory access request, wherein the controller is further configured to:
read cached data at the second location (Agombar, [0006], performs an XOR (exclusive OR) operation on the new data and the old data to yield a parity delta; [0034], Because this data 300 a resides in cache 216, if and when the data 300 a is overwritten, parity delta information 302 b may be readily calculated using the old data 300 a and the new incoming data 300 b prior to overwriting the old data 300 a; Note – old data in the cache needs to be read in order to perform an XOR operation); and
read parity data stored in the one or more of the number of memory devices (Agombar, [0036], when the new data 300 b is destaged to the RAID layer 306 so that it can be written to the RAID 310 … apply the parity delta 400 to a parity value in the stride 600; [0037], The RAID layer 306 further applies the parity delta 400 received from the cache 216 to the parity value 602 in the stride 600. This may be accomplished by XORing the parity delta 400 with the parity value 602.), wherein the parity data is read from the memory device in the absence of reading data corresponding to the parity data stored in the one or more of the number of memory devices (Agombar, [0034], when data is destaged from a cache 216 to a RAID 310, a copy of the data often remains in the cache 216 in the event it is needed again. Because this data 300 a resides in cache 216, if and when the data 300 a is overwritten, parity delta information 302 b may be readily calculated using the old data 300 a and the new incoming data 300 b prior to overwriting the old data 300 a … When the new data 300 b is destaged, the new data 300 b may be written to the RAID 310 and the parity delta 302 b may be applied to (e.g., XORed with) the parity value of the stride containing the new data 300 b. This will reduce or eliminate the need to read data from the RAID 310 to calculate the new parity value).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Park to incorporate teachings of Agombar to generate a parity delta value by using old user data stored in a cache instead of reading the old user data from a storage device during a cache de-staging operation. A person of ordinary skill in the art would have been motivated to combine the teachings of Park with Agombar because it improves efficiency and performance of the storage system disclosed in Park by eliminating a read operation for retrieving old data from a storage device during a cache de-staging operation, which reduces I/O latency for the storage system.
The combination of Park teaches writing back data from a cache to a storage device, nevertheless, the combination of Park does not explicitly teach perform a cache write-back operation in response to receiving the further memory access request, as claimed.
However, the combination of Park in view of Kim teaches perform a cache write-back operation in response to receiving the further memory access request (Kim, [0203], when the command pattern is a write pattern, flushing all or part of the data stored in a write buffer WR_BUF, which stores data write-requested by the host HOST, into the memory device 110 in order to process the write command received from the host HOST.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Park to incorporate teachings of Kim to include a flush command from a host to instruct a controller to perform a flush operation. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Park with Kim because it improves efficiency and communication of the storage system disclosed in the combination of Park by allowing a host to issue commands to control I/O memory accesses in a storage device.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Park, Agombar, and Kim as applied to claim 1 above, and further in view of Jeong (US 2022/0350528), hereinafter Jeong.
Regarding claim 3, the combination of Park teaches all the features with respect to claim 1 as outlined above. The combination of Park does not explicitly teach the apparatus of claim 1, wherein caching the data in the first location in the cache is performed substantially contemporaneously with caching the data in the second location in the cache, as claimed.
However, the combination of Park in view of Jeong teaches the apparatus of claim 1, wherein caching the data in the first location in the cache is performed substantially contemporaneously with caching the data in the second location in the cache (Jeong, [0129], The write buffer 230 may include a first memory 260 and a second memory 270; [0183]; claim 19, The memory storage device of claim 17, wherein the first buffer memory and the second buffer memory are configured to store the data at the same time.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Park to incorporate teachings of Jeong to store write data to a first location in a cache and a second location in the cache at the same time. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Park with Jeong because it improves efficiency and performance of the storage system disclosed in the combination of Park by allowing a second cache to provide requested data to a read operation.
Claim(s) 10 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Park, Agombar, and Kim as applied to claims 7 and 11 respectively above, and further in view of Ebara et al. (US2020/0034263), hereinafter Ebara.
Regarding claim 10, the combination of Park teaches all the features with respect to claim 7 as outlined above. The combination of Park does not explicitly teach the method of claim 7, further comprising performing a cache eviction operation on the first cache, the second cache, or both, responsive to receiving the further memory access request, as claimed.
However, the combination of Park in view of Ebara teaches the method of claim 7, further comprising performing a cache eviction operation on the first cache, the second cache, or both, responsive to receiving the further memory access request (Ebara, [0144], Then, the data management program (282) releases a use area of the data to be destaged from the cache memory (121) (S403)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Park to incorporate teachings of Ebara to perform a flush/write-back operation by using data read from a cache and parity data retrieved from a storage device. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Park with Ebara because it improves reliability of the storage system disclosed in the combination of Park by storing parity data associated with user data in order to restore user data when needed.
Regarding claim 12, the combination of Park teaches all the features with respect to claim 11 as outlined above. The combination of Park does not explicitly teach the apparatus of claim 11, wherein the controller is further configured to manage the cache in accordance with a write-back cache writing policy, as claimed.
The combination of Park in view of Ebara teaches the apparatus of claim 11, wherein the controller is further configured to manage the cache in accordance with a write-back cache writing policy (Ebara, [0135], write-back write processing).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Park to incorporate teachings of Ebara to perform a flush/write-back operation by using data read from a cache and parity data retrieved from a storage device. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Park with Ebara because it improves reliability of the storage system disclosed in the combination of Park by storing parity data associated with user data in order to restore user data when needed.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Park, Agombar, and Kim as applied to claim 11 above and in view of Wallach (US 2021/0034531), hereinafter Wallach.
Regarding claim 13, the combination of Park teaches all the features with respect to claim 11 as outlined above. The combination of Park does not explicitly teach the apparatus of claim 11, wherein the cache further comprises a set-associative cache including a plurality of cache lines, as claimed.
However, the combination of Park in view of Wallach teaches the apparatus of claim 11, wherein the cache further comprises a set-associative cache including a plurality of cache lines (Wallach, [0036], a cache of the set of caches can be designed in multiple ways, and one of those ways includes a cache of a set divided into cache sets through cache set associativity (which can include physical or logical cache set associativity)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Park to incorporate teachings of Wallach to divide a cache into cache sets through cache set associativity. A person of ordinary skill in the art would have been motivated to combine the teachings of Park with Wallach because it improves efficiency of the storage system disclosed in Park by allowing a single cache with set associativity to have multiple cache sets within the single cache and the different parts of the single cache (i.e. cache sets) can be allocated for different use (Wallach, [0036]).
Claim(s) 14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Park, Agombar, and Kim as applied to claim 11 above and in view of Nellans et al. (US 2012/0079174), hereinafter Nellans and Byun (US 2022/0107757), hereinafter Byun.
Regarding claim 14, the combination of Park teaches all the features with respect to claim 11 as outlined above. The combination of Park does not explicitly teach the apparatus of claim 11, further comprising: interface management circuitry; data management circuitry coupled to the interface management circuitry, wherein the data management circuitry includes: error detection circuitry configured to perform error detection operations on the data; and error correction circuitry coupled to the error detection circuitry and configured to perform error correction operations on the data; and redundant array of independent disks (RAID) circuitry coupled to the error detection circuitry and configured to perform a recovery operation on the data, as claimed.
However, the combination of Park in view of Nellans teaches wherein the data management circuitry includes: error detection circuitry configured to perform error detection operations on the data (Nellans, Fig. 3, ECC Generator 304); and
error correction circuitry coupled to the error detection circuitry and configured to perform error correction operations on the data (Nellans, Fig.3, ECC Correction Module 322); and
redundant array of independent disks (RAID) circuitry coupled to the error detection circuitry and configured to perform a recovery operation on the data (Nellans, [0139], the solid-state storage controller 104 stores data using some type of RAID and is able to recover the corrupted data)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Park to incorporate teachings of Nellans to include ECC components, RAID memory, and bank controller to controller 1200. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Park because it improves efficiency and reliability of the storage system disclosed in the combination of Park by include error detection and correction components to verify and correct data.
The combination of Park does not explicitly teach interface management circuitry, as claimed.
However, the combination of Park in view of Byun teaches a host interface management circuity (Byun, [0083], The host interface 211 may include a command processor 2111 … and a first DMA engine 2117).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Park to incorporate teachings of Byun to include a command processor and a DMA engine in a host interface of a storage controller. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of the combination of Park with Byun because it improves efficiency of the storage system disclosed in the combination of Park by having components to manage received host command and host data (Byun, [0084], [0087]).
Regarding claim 16, the combination of Park teaches all the features with respect to claim 14 as outlined above. The combination of Park further teaches the apparatus of claim 14, wherein the cache includes a first cache and a second cache; and wherein: the first location is in the first cache; and the second location is the second cache (Park, [0063], the cache group 420 may include at least three caches 1CAH, 2CAH, and 3CAH).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Park, Agombar, Kim, Nellans and Byun as applied to claim 14 above and in view of Wallach (US 2021/0034531), hereinafter Wallach.
Regarding claim 15, the combination of Park teaches all the features with respect to claim 14 as outlined above. The combination of Park does not teach the apparatus of claim 14, wherein the cache is an individual cache, and wherein: the first location is associated with a first logical portion of the individual cache; and the second location is associated with a second logical portion of the individual cache, as claimed.
However, the combination of Park in view of Wallach teaches the apparatus of claim 14, wherein the cache is an individual cache, and wherein: the first location is associated with a first logical portion of the individual cache; and the second location is associated with a second logical portion of the individual cache (Wallach, [0036], different parts of the single cache can be allocated for use by the processor without allocating the entire cache; [0055], copy the portion of content cached in the first cache set to the second cache set).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Park to incorporate teachings of Wallach to divide a single cache into different cache sets so that the cache sets can be used for different purpose. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Park with Wallach because it improves efficiency of the storage system disclosed in the combination of Park by allowing different parts of a single cache to be allocated for use by a processor without allocating the entire cache (Wallach, [0036]).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Park, Agombar, Kim, Nellans, and Byun as applied to claim 16 above and in view of Yano et al. (US 2006/0293831), hereinafter Yano.
Regarding claim 17, the combination of Park teaches all the features with respect to claim 16 as outlined above. The combination of Park does not explicitly teach the apparatus of claim 16, wherein the first location in the first cache has the same physical address as a corresponding physical address of the second location in the second cache, as claimed.
However, the combination of Park in view of Yano teaches the apparatus of claim 16, wherein the first location in the first cache has the same physical address as a corresponding physical address of the second location in the second cache (Yano, [0079], The self-monitor 113 samples data (i.e., the result of computation) out of a selected one of addresses in the data RAM and data (i.e., an expected value) out of a corresponding one of addresses or the same address in the mirror RAM and compares them to determine whether the data in the data RAM is coincident with that in the mirror RAM or not. If not, the self-monitor 113 determines that the controller 112 is failing to produce the drive command to be outputted to the driver circuit 130; Note – the combination of Park teaches a primary cache and a backup (i.e. mirror) cache are located inside of a memory controller.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Park to incorporate teachings of Yano to store same data at the same address for both a primary cache and its backup cache. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Park with Yano because it improves efficiency and performance of the storage system disclosed in the combination of Park by accessing same data using the same address in two different caches for fast searching/mapping same data in two different caches.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Park, Agombar, Kim, Nellans, and Byun as applied to claim 16 above and in view of Flynn (US 2011/0022801), hereinafter Flynn.
Regarding claim 18, the combination of Park teaches all the features with respect to claim 16 as outlined above. The combination of Park does not explicitly teach the apparatus of claim 16, wherein the first location in the first cache has the same logical address as a corresponding logical address of the second location in the second cache, as claimed.
However, the combination of Park in view of Flynn teaches the apparatus of claim 16, wherein the first location in the first cache has the same logical address as a corresponding logical address of the second location in the second cache (Flynn, [0210]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Park to incorporate teachings of Flynn to use same logical address to identify same data in different caches. A person of ordinary skill in the art would have been motivated to combine the teaching of Park with Flynn because it improves performance of the storage system disclosed in Park by identifying same data using the same address in two different caches and allowing easy searching/mapping the same data in two different caches (Flynn, [0210]).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Park, Agombar, Kim, Nellans, and Byun as applied to claim 16 above and in view of Hong et al. (US 2018/0063512), hereinafter Hong.
Regarding claim 19, the combination of Park teaches all the features with respect to claim 16 as outlined above. The combination of Park does not explicitly teach the apparatus of claim 16, further comprising a first buffer coupled to the first cache, and a second buffer coupled to the second cache, wherein the data management circuity is configured to buffer the data in the first buffer and the second buffer, as claimed.
However, the combination of Park in view of Hong teaches the apparatus of claim 16, further comprising a first buffer coupled to the first cache, and a second buffer coupled to the second cache, wherein the data management circuity is configured to buffer the data in the first buffer and the second buffer (Hong, [0170]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Park to incorporate teachings of Hong to couple a first cache to a first buffer and a second cache to a second buffer. A person of ordinary skill in the art would have been motivated to combine the teachings of Park with Hong because it improves efficiency of the storage system by grouping and processing similar data together for a specific purpose.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Park, Agombar, and Kim as applied to claim 11 above and in view of Roy (US 2021/0157521), hereinafter Roy.
Regarding claim 20, the combination of Park teaches all the features with respect to claim 11 as outlined above. The combination of Park does not explicitly teach the apparatus of claim 11, wherein the controller is further configured to transmit additional data associated with an additional memory access request to cache the additional data in the cache in the absence of modification of the data at the second location in the cache, as claimed.
However, the combination of Park in view Roy teaches the apparatus of claim 11, wherein the controller is further configured to transmit additional data associated with an additional memory access request to cache the additional data in the cache in the absence of modification of the data at the second location in the cache (Roy, claim 2, an update request to update the data entity or a write request to replace the data entity; Note – an update request has different signal from an write request and the data associated with an write request is cached in the absence of modification of the data).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Park to incorporate teachings of Roy to separate update requests from new data write requests so that new data is cached differently from update data. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Park because it improves efficiency and reliability of the storage system by separating update requests from new write requests when the requests need to be processed differently.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2022/0317920), hereinafter Park in view of Byun (US 2022/0107757), hereinafter Byun, and further in view of Parker et al. (US 2021/0397383), hereinafter Parker, Agombar et al. (US2018/0095824), hereinafter Agombar, and Kim (US2023/0063280), hereinafter Kim.
Regarding claim 7, Park teaches a method, comprising:
receiving a memory access request from a host by interface management circuitry of a controller (Park, [0053], the controller 1200 may include a host interface 510; [0054], during a program operation, the host interface 510 may receive a program request, a logical address, and write data from the host 2000) configured for a Compute Express Link (CXL) protocol and coupled to a memory device;
storing data corresponding to the memory access request in a first location in a first cache included in the memory controller (Park, [0064], first cache; Fig. 5, see cache 420 is located within memory controller 1200);
storing the data corresponding to the memory access request in a second location in a second cache included in the memory controller (Park, [0064], during the program operation, first data 1DATA may be data output from the host 2000, and may be temporarily stored in the first cache 1CAH and then transmitted to the third cache 3CAH);
receiving a further memory access request (Park, [0005], a controller configured to in response to a program request or a read request for a selected memory block among the memory blocks being received from a host); and
performing a cache write-back operation in response to receiving the further memory access request by:
transmitting a signal associated with a read operation to read cached data at the second location; and
transmitting a signal to read parity data stored in the memory device, wherein the signal to read the parity data is transmitted to the memory device in the absence of transmitting a signal associated with a read operation to read data corresponding to the parity data stored in the memory device..
Park does not explicitly teach an interface management circuitry of a controller configured for a Compute Express Link (CXL) protocol and coupled to a memory device; performing a cache write-back operation in response to receiving the further memory access request by: transmitting a signal associated with a read operation to read cached data at the second location; and transmitting a signal to read parity data stored in the memory device, wherein the signal to read the parity data is transmitted to the memory device in the absence of transmitting a signal associated with a read operation to read data corresponding to the parity data stored in the memory device, as claimed.
However, Park in view of Byun teaches a host interface management circuity (Byun, [0083], The host interface 211 may include a command processor 2111 … and a first DMA engine 2117).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Park to incorporate teachings of Byun to include a command processor and a DMA engine in a host interface of a storage controller. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Park with Byun because it improves efficiency of the storage system disclosed in Park by managing received host commands and host data using a host interface (Byun, [0084], [0087]).
The combination of Park does not explicitly teach a controller configured for a Compute Express Link (CXL) protocol and coupled to a memory device; performing a cache write-back operation in response to receiving the further memory access request by: transmitting a signal associated with a read operation to read cached data at the second location; and transmitting a signal to read parity data stored in the memory device, wherein the signal to read the parity data is transmitted to the memory device in the absence of transmitting a signal associated with a read operation to read data corresponding to the parity data stored in the memory device, as claimed.
However, the combination of Park in view of Parker teaches a memory controller configured for a Compute Express Link (CXL) protocol and coupled to a memory device (Parker, [0022]; Fig.1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Park to incorporate teachings of Park to include Compute Express Link protocol as one of the protocols that host interrace may operate under. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Park with Parker because it improves performance the storage system disclosed in the combination of Park by allowing low-latency connectivity and ensuring memory coherency.
The combination of Park does not explicitly teach performing a cache write-back operation in response to receiving the further memory access request by: transmitting a signal associated with a read operation to read cached data at the second location; and transmitting a signal to read parity data stored in the memory device, wherein the signal to read the parity data is transmitted to the memory device in the absence of transmitting a signal associated with a read operation to read data corresponding to the parity data stored in the memory device, as claimed.
However, the combination of Park in view of Agombar teaches receiving a further memory access request ((Agombar, [0006], receiving a write request comprising new data for overwriting corresponding old data in cache); and
performing a cache write-back operation (Agombar, [0034], When the new data 300 b is destaged) in response to receiving the further memory access request by:
transmitting a signal associated with a read operation to read cached data at the second location (Agombar, [0006], performs an XOR (exclusive OR) operation on the new data and the old data to yield a parity delta; [0034], Because this data 300 a resides in cache 216, if and when the data 300 a is overwritten, parity delta information 302 b may be readily calculated using the old data 300 a and the new incoming data 300 b prior to overwriting the old data 300 a; Note – old data in the cache needs to be read in order to perform an XOR operation); and
transmitting a signal to read parity data stored in the memory device (Agombar, 0036], when the new data 300 b is destaged to the RAID layer 306 so that it can be written to the RAID 310 … apply the parity delta 400 to a parity value in the stride 600; [0037], In this example … The RAID layer 306 further applies the parity delta 400 received from the cache 216 to the parity value 602 in the stride 600. This may be accomplished by XORing the parity delta 400 with the parity value 602.), wherein the signal to read the parity data is transmitted to the memory device in the absence of transmitting a signal associated with a read operation to read data corresponding to the parity data stored in the memory device (Agombar, [0034], when data is destaged from a cache 216 to a RAID 310, a copy of the data often remains in the cache 216 in the event it is needed again. Because this data 300 a resides in cache 216, if and when the data 300 a is overwritten, parity delta information 302 b may be readily calculated using the old data 300 a and the new incoming data 300 b prior to overwriting the old data 300 a … When the new data 300 b is destaged, the new data 300 b may be written to the RAID 310 and the parity delta 302 b may be applied to (e.g., XORed with) the parity value of the stride containing the new data 300 b. This will reduce or eliminate the need to read data from the RAID 310 to calculate the new parity value).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Park to incorporate teachings of Agombar to generate a parity delta value by using old user data stored in a cache instead of reading the old user data from a storage device during a cache de-staging operation. A person of ordinary skill in the art would have been motivated to combine the teachings of Park with Agombar because it improves efficiency and performance of the storage system disclosed in Park by eliminating a read operation for retrieving old data from a storage device during a cache de-staging operation, which reduces I/O latency for the storage system.
The combination of Park teaches writing back data from a cache to a storage device, nevertheless, the combination of Park does not explicitly teach perform a cache write-back operation in response to receiving the further memory access request, as claimed.
However, the combination of Park in view of Kim teaches perform a cache write-back operation in response to receiving the further memory access request (Kim, [0203], when the command pattern is a write pattern, flushing all or part of the data stored in a write buffer WR_BUF, which stores data write-requested by the host HOST, into the memory device 110 in order to process the write command received from the host HOST.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Park to incorporate teachings of Kim to include a flush command from a host to instruct a controller to perform a flush operation. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Park with Kim because it improves efficiency and communication of the storage system disclosed in the combination of Park by allowing a host to issue commands to control I/O memory accesses in a storage device.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Park, Byun, Parker, Agombar, and Kim as applied to claim 7 above, and further in view of Jeong (US 2022/0350528),hereinafter Jeong.
Regarding claim 8, the combination of Park teaches all the features with respect to claim 7 as outlined above. The combination of Park does not explicitly the method of claim 7, further comprising: transmitting a further signal indicative of additional data associated with the further memory access request to the first cache to cache the additional data in the first cache, wherein transmitting the further signal occurs in the absence of transmission of a signal indicative of the additional data to the second cache, as claimed.
However, the combination of Park in view of Jeong teaches the method of claim 7, further comprising: transmitting a further signal indicative of additional data associated with the further memory access request to the first cache to cache the additional data in the first cache, wherein transmitting the further signal occurs in the absence of transmission of a signal indicative of the additional data to the second cache (Jeong, [0131], The first memory 260 may cache the data DATA. The first memory 260 may temporarily store the data DATA in a memory device corresponding to a first cache ID C_ID1. The first cache ID C_ID1 may correspond to an address of the first memory 260, in which the data DATA is stored. The memory controller 200 buffers the data DATA only in the first memory 260, and does not buffer the data DATA in the second memory 270. ).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Park to incorporate teachings of Jeong to store write data to a first location in a cache and a second location in the cache at the same time. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Park with Jeong because it improves efficiency and performance of the storage system disclosed in the combination of Park by allowing a second cache to provide requested data to a read operation.
Regarding claim 9, the combination of Park teaches all the features with respect to claim 8 as outlined above. The combination of Park further teaches the method of claim 8, further comprising:
performing an operation to determine updated parity data based on: the parity data; the cached data from the second location in the second cache; and the additional data (Agombar, [0034], if and when the data 300 a is overwritten, parity delta information 302 b may be readily calculated using the old data 300 a and the new incoming data 300 b prior to overwriting the old data 300 a. The parity delta 302 b may be stored in cache 216 along with the new data 300 b, and destaged from the cache 216 along with the new data 300 b. When the new data 300 b is destaged, the new data 300 b may be written to the RAID 310 and the parity delta 302 b may be applied to (e.g., XORed with) the parity value of the stride containing the new data 300 b);
transmitting a signal to store the additional data in the memory device (Agombar, [0036], The RAID layer 306 may write the new data 300 b to the RAID 310; Park, [0054]; Kim, [0203]); and transmitting a signal to store the updated parity data in the memory device (Agombar, [0037], This may be accomplished by XORing the parity delta 400 with the parity value 602. This updates the parity value 602 to reflect the newly written data 300 b in the stride 600).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Park to incorporate teachings of Agombar to transmit signals to store new user and updated parity data in a storage device. A person of ordinary skill in the art would have been motivated to combine the teachings of Park with Agombar because it improves efficiency and performance of the storage system disclosed in Park by elimination a read operation for retrieving old data from a storage device and a write operation for writing the retrieved old data in a cache/buffer in order to generate a parity data.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gupta et al. (US2019/0317898) teaches cache de-stage operations using updated user data and old parity data.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NANCI N WONG/ Primary Examiner, Art Unit 2137