Prosecution Insights
Last updated: April 19, 2026
Application No. 18/830,459

ENHANCED NEGATIVE ACKNOWLEDGMENT CONTROL FRAME

Non-Final OA §103
Filed
Sep 10, 2024
Examiner
CHASE, SHELLY A
Art Unit
2112
Tech Center
2100 — Computer Architecture & Software
Assignee
Micron Technology, Inc.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
98%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allow Rate
715 granted / 755 resolved
+39.7% vs TC avg
Minimal +3% lift
Without
With
+3.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
17 currently pending
Career history
772
Total Applications
across all art units

Statute-Specific Performance

§101
13.2%
-26.8% vs TC avg
§103
38.2%
-1.8% vs TC avg
§102
15.8%
-24.2% vs TC avg
§112
15.9%
-24.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 755 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1 to 21 are presented for examination. The preliminary amendment filed 11-20-2024 canceled claim 1 and added new claims 2 to 21. Information Disclosure Statement The references listed in the information disclosure statement submitted on 11-20-2024 have been considered by the examiner (see attached PTO-1449). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2, 7, 9, 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Hamo et al. (USPAP 2016/0170824). Claim 2, 9 and 16: Hamo substantially teaches the claimed invention. Hamo teaches a system including a memory device (140) coupled to a host (110) via of an interconnect (130) wherein the memory device may include one or more integrated circuit (IC) die and any type of memory technology (see par. 00210). Hamo teaches that communication between the host and the memory is based on a UniProSM standard by way of a protocol stack (110) in host and a protocol stack (150) in the memory device (see par. 0023). Hamo teaches that the protocol stack comprises a physical layer, an adapter layer, a data link layer, a network layer and a transport layer (see fig. 1 and par. 0025 et seq.). Hamo teaches that the system communicates to the memory device one or more frames (132) via of the interconnect and through a processor to detect any errors associated with receiving the one or more frames (see par. 0026). Hamo teaches that the protocol stack of the memory device may process packets from host to provide access to memory array (170) via operation of access logic (175) (see par. 0027). Hamo teaches that detection of error associated with the frame results in the generation of NAC message (134) and NAC message includes two components with the first component representing a negative acknowledgement and the second component comprising an error code or other identifier for the detected error (see par. 0027). Hamo teaches a memory device receiving a data frame from the host coupled to the memory device and that one or more data frames have a structure of a header portion and a payload portion (see fig. 5, par. 0030 and par. 0042). Hamo teaches that the errors detected may relate to a format of the data frame, content of the data frame, and/or a state of hardware to receive or otherwise process the data frame. Hamo teaches that a frame evaluation logic, detects errors based on a cyclic redundancy check (CRC) information included in the data frame (see par. 0032). Hamo teaches that the errors detected are adapted for a UniProSM standard and that frame processing and generating may include operation specified in a UniProSM standard which comprises a set a physical layer, a physical adapter layer, a data link layer, a network layer, and a transport layer (see fig. 2 and par. 0033 et seq.). Hamo teaches that the physical adapter indicates an error based on the received physical symbol, I.e., if a correct exception physical (PHY) symbol was received or a correct exception PHY symbol was received immediately after another exception PHY symbol (see par. 0039). Hamo teaches that when an error is detected, transmitting a NAC control frame that is generated by a frame generator (346) (see par. 0034). Hamo also teaches that the NAC message may include operations adapted from conventional UniProSM techniques such as communicating an identifier of an error type (see par. 0034). Hamo teaches that the frame generator may generate a NAC message that includes bot a value that classifies the NAC message as negative acknowledgement and an error identifier that specifies a particular type of error that is the cause of the NAC message (see par. 0035). Hamo teaches sending the NAC message from the memory device by frame generator to a host via of MPHY Tx (332) (see par. 0035). Hamo fails to teach or fairly suggest or render obvious the combination of elements with the novel element of “determining an error condition associated with a set of layers of a protocol stack based at least in part on the data payload of the data frame;” however, this teaching is obvious to the teachings of Hamo because Hamo teaches a method for quickly identifying errors of transmitted data communicated between a memory device and a host based on a protocol stack utilizes determining a type of error based on the format of the data frame. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus having circuitry that sends a NAC message from a memory device to a host when an error is detected of Hamo to include the limitation of “determining an error condition associated with a set of layers of a protocol stack based at least in part on the data payload of the data frame” because Hamo teaches a method and an apparatus for error handling to quickly identify any problems of the transmitted data are based on the detection of errors due to a format of the data frame as well as adapted for the UniProSM standard that supports a protocol stack. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a method and an apparatus for error handling that utilizes the UniProSM standards that supports communication NAC messages based on the types of errors detected to quickly identify errors in the transmitted data as taught by Hamo (see par. 0019 et seq.). As per claims 7 and 14, Hamo teaches that the protocol stack is based on a UniPro SM standard (see par. 0024). Allowable Subject Matter Claims 3 to 6, 8, 10-13, 15, and 17 to 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Pan et al. (USPAP 2023/0291688) discloses a data transmission method and electronic device. Radulescu (WO 2012052487 A1) discloses a system and method for high-speed serial communication transceiver. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHELLY A CHASE whose telephone number is (571)272-3816. The examiner can normally be reached Mon-Thu 8:00-5:30, 2nd Friday 8:00-4:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at 571-272 3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Shelly A Chase/ Primary Examiner, Art Unit 2112
Read full office action

Prosecution Timeline

Sep 10, 2024
Application Filed
Dec 27, 2025
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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BLOCK HEALTH DETECTOR FOR BLOCK RETIREMENT IN A MEMORY SUB-SYSTEM
2y 5m to grant Granted Apr 14, 2026
Patent 12603753
SIGNAL TRANSMITTING METHOD, ELECTRONIC DEVICE, AND COMMUNICATION SYSTEM
2y 5m to grant Granted Apr 14, 2026
Patent 12596610
PARITY DATA IN DYNAMIC RANDOM ACCESS MEMORY (DRAM)
2y 5m to grant Granted Apr 07, 2026
Patent 12572413
MEMORY CONTROLLERS AND MEMORY SYSTEMS
2y 5m to grant Granted Mar 10, 2026
Patent 12572412
MANAGING ERROR CORRECTIONS FOR DATA STORAGE SYSTEMS
2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
98%
With Interview (+3.3%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 755 resolved cases by this examiner. Grant probability derived from career allow rate.

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