Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Examiner cites particular columns or paragraphs, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Species A in the reply filed on 2/10/2026 is acknowledged.
Claims 26-48 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/10/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 and 13-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2017/0294159).
Regarding claim 1, Lee discloses a sensing unit (see sensing unit in Figs. 2-4; para[0013]-para[0014]) comprising:
a sensing line receiving a pixel current from a pixel (see in Figs. 1-4 sensing lines 14B receiving a pixel current Ip; para[0057]);
a current sink unit connected to the sensing line and receiving a sink current from
the sensing line (see in Figs. 2-4, 6 and 8 current sink circuit SINK receiving a sink current Is; para[0057]); and
a current integrator connected to the sensing line and generating an output
voltage using a control current supplied from the sensing line (see in Figs. 2-4, 6 and 8 current integrator CI connected to the sensing line 14B and generating an output voltage Vout using a control current Ip-Is, that is, the pixel current Ip fed from the sensing line 14B reduced by the sink current Is; para[0057]-para[0058]),
wherein the current sink unit changes a current amount of the sink current in
response to the output voltage (regarding Figs. 4-6 and 8, “The sensing unit can further include a sink current control part CCB that controls the amount of sink current Is”, “based on a digital sensed value SD output from the ADC”, which is based on Vout since “the output Vout of the current integrator CI changes to an integrated value Vsen, which is a voltage, through the feedback capacitor Cfb”, and “The integrated value Vsen is converted into a digital sensed value SD in the ADC”; para[0014]; para[0051]; para[0061]; para[0065]-para[0066]; para[0068]; para[0074]; para[0077]; para[0083]).
Regarding claim 2, Lee discloses all the claim limitations as applied above (see claim 1). In addition, Lee discloses the control current corresponds to a difference between the pixel current and the sink current (see in Figs. 2-4 current integrator CI connected to the sensing line 14B receives control current Ip-Is, that is, the pixel current Ip fed from the sensing line 14B reduced by the sink current Is; para[0057]-para[0058]).
Regarding claim 3, Lee discloses all the claim limitations as applied above (see claim 1). In addition, Lee discloses when the pixel current is greater than the sink current, the output voltage decreases, and the current sink unit increases the sink current in response to the output voltage (“Referring to FIG. 12, the amount of sink current Is increases as the amount of pixel current Ip increases” to compensate for a decrease in Vout (see Fig. 4), in order to keep “the potential difference at the output terminal of the integrator—that is, the voltage difference ΔV between the reference voltage Vpre and the integrated value Vsen—” at a desired constant value; para[0084]-para[0085]).
Regarding claim 4, Lee discloses all the claim limitations as applied above (see claim 1). In addition, Lee discloses when the pixel current is less than the sink current, the output voltage increases, and the current sink unit decreases the sink current in response to the output voltage (since, “Referring to FIG. 12, the amount of sink current Is increases as the amount of pixel current Ip increases”, it is clear that when the pixel current Ip is less the sink current Is, Vout increases (see Fig. 4), and accordingly, SINK reduces the sink current Is, to compensate for the increase in Vout, in order to keep “the potential difference at the output terminal of the integrator—that is, the voltage difference ΔV between the reference voltage Vpre and the integrated value Vsen—” at a desired constant value; para[0084]-para[0085]).
Regarding claim 5, Lee discloses all the claim limitations as applied above (see claim 1). In addition, Lee discloses when the pixel current and the sink current are same, the output voltage maintains a constant voltage (since, “Referring to FIG. 12, the amount of sink current Is increases as the amount of pixel current Ip increases”, it is clear that when the pixel current Ip is equal to the sink current Is, “the potential difference at the output terminal of the integrator—that is, the voltage difference ΔV between the reference voltage Vpre and the integrated value Vsen—” (Vout) is kept at a constant voltage (see Fig. 4); para[0084]-para[0085]).
Regarding claim 6, Lee discloses all the claim limitations as applied above (see claim 5). In addition, Lee discloses a voltage storage unit storing the output voltage (see sampling part SH in Figs. 2-4, 6 and 8; “The sampling part SH samples and holds the integrated value from the current integrator CI”; para[0051]); and
an analog to digital converter generating sensing data using the output voltage stored in the voltage storage unit (see analog-to-digital converter (ADC) in Figs. 2-4, 6 and 8; “The ADC performs analog-to-digital conversion of the integrated value from the sampling part SH to produce a digital sensed value SD”; para[0051]).
Regarding claim 7, Lee discloses all the claim limitations as applied above (see claim 6). In addition, Lee discloses the voltage storage unit comprises:
an input switch and an output switch connected in series between an output
terminal of the current integrator and the analog to digital converter (see input switch SW2 and output switch SW3 in Fig. 4; para[0059]); and
a holding capacitor connected between a common terminal of the input switch
and the output switch, and a ground potential (see holding capacitor Ch in Fig. 4, “connected between the third and second switches SW2 and SW3, and the other end is connected to a ground voltage source GND”; para[0059]).
Regarding claim 8, Lee discloses all the claim limitations as applied above (see claim 1). In addition, Lee discloses the current integrator comprises:
an operational amplifier of which an inverting input terminal is connected to the
sensing line and of which a non-inverting input terminal receives a voltage of reference
power (see OP amplifier AMP in Fig. 4 “has an inverting input terminal (−) that is connected to the sensing line 14B and receives the adjusted current Ip−Is, [and] a non-inverting input terminal (+) that receives a reference voltage Vpre”; para [0058]);
a feedback capacitor connected between the inverting input terminal and an
output terminal of the operational amplifier (see in Fig. 4, “feedback capacitor Cfb… connected between the inverting input terminal (−) and output terminal of the OP amplifier AMP”; para[0058]); and
a reset switch connected in parallel with the feedback capacitor between the
inverting input terminal and the output terminal of the operational amplifier (see in Fig. 4, “first switch SW1… connected to both ends of the feedback capacitor Cfb”; para[0058]).
Regarding claims 13-18 and 20-21, these claims are analogous to claims 1-8, respectively, except these are display device claims (see display device in Figs. 1-4; para[0021]), and therefore, are rejected for the same reasons as claims 1-8 above.
Regarding claim 19, Lee discloses all the claim limitations as applied above (see claim 18). In addition, Lee discloses the analog to digital converter is connected to a plurality of sensing channels (see analog-to-digital converter (ADC) connected to a plurality of sensing channels as shown in Figs. 2-3, 6 and 8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2017/0294159), in view of Chaji (US 2017/0039939).
Regarding claim 9, Lee discloses all the claim limitations as applied above (see claim 1). In addition, Lee discloses a first switch connected between the sensing line and the current integrator (see switch SWa in Fig. 8). However, Lee does not appear to expressly disclose a second switch connected between a common node between the first switch and the current integrator, and the current sink unit.
Chaji discloses a second switch connected between a common node between a first switch and a current integrator, and a reference current unit (see switch 273 in Fig. 2A; para[0042]; para[0046]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Lee’s invention, with the teachings in Chaji’s invention, to have a second switch connected between a common node between the first switch and the current integrator, and the current sink unit, for the advantage of time multiplexing the input of the integrator between the reference/sink current and the pixel current (para[0046]).
Regarding claim 22, it is analogous to claim 9, and therefore it is rejected for the same reasons as claim 9 above.
Claim(s) 10, 12, 23 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2017/0294159), in view of Chung (US 2012/0169704).
Regarding claim 10, Lee discloses all the claim limitations as applied above (see claim 1). However, Lee does not appear to expressly disclose a current source unit connected to the sensing line and configured to supply a source current to the sensing line.
Chung discloses a current source unit connected to a sensing line and configured to supply a source current to the sensing line (see current source 77 in Fig. 2B, connected to sensing line Am to supply a source current to sensing line Am; para[0071]; para[0074]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Lee’s invention, with the teachings in Chung’s invention, to have a current source unit connected to the sensing line and configured to supply a source current to the sensing line, for the advantage of detecting and optimizing a driving voltage variable by the performance characteristic of the OLED of the pixel (para[0003]; para[0013]; para[0074]).
Regarding claim 12, Lee and Chung disclose all the claim limitations as applied above (see claim 10). In addition, the combination already discloses the control current corresponds to a value obtained by subtracting the sink current from a sum of the pixel current and the source current (see e.g. in Fig. 4, Lee discloses the current integrator CI connected to the sensing line 14B receives control current corresponding to the pixel current Ip fed from the sensing line 14B reduced by the sink current Is, which is increased by the source current supplied to the sensing line as a result of the combination with Chung).
Regarding claims 23 and 25, these claims are analogous to claims 10 and 12, respectively, and therefore are rejected for the same reasons as claims 10 and 12 above.
Claim(s) 11 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2017/0294159), in view of Chung (US 2012/0169704), and further in view of Kato et al. (US 5,060,178).
Regarding claim 11, Lee and Chung disclose all the claim limitations as applied above (see claim 10). However, Lee and Chung do not appear to expressly disclose the current source unit controls a current amount of the source current in response to the output voltage.
Kato discloses a current source unit controls a current amount of a source current in response to an output voltage (as shown in Fig. 6, current source 17 controls a source current amount based on an output voltage from integrator M; see column 4, line 65, to column 5, line 31; see column 5, line 55, to column 6, line 6).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Lee’s and Chung’s combination, with the teachings in Kato’s invention, to have the current source unit controls a current amount of the source current in response to the output voltage, for the advantage of obtaining a signal processing apparatus which causes no noise in change of a data processing mode and upon power supply (column 3, lines 21-23).
Regarding claim 24, it is analogous to claim 11, and therefore it is rejected for the same reasons as claim 11 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GLORYVID FIGUEROA-GIBSON whose telephone number is (571)272-5506. The examiner can normally be reached on 9am-5pm, Monday -Friday, Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached on 571-272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GLORYVID FIGUEROA-GIBSON/Patent Examiner, Art Unit 2628
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628
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