Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Drawing
The drawings filed on 09/11/2024 are acceptable.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/09/2025 is in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has been considered by the examiner.
Claims 1-30 are pending and have been examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-11, 14, 16 and 20-26 are rejected under 102(a)(2) as being anticipated by Kim et al. (US 2023/0180363 A1), hereinafter ‘Kim.
In re to claim 1, Kim disclose a current driver (i.e. 100, fig. 1, see par. [0030]) having an input channel (i.e. the channel of Iref) and an output channel (i.e. the channel of Io), comprising: a current source (i.e. 110), deployed in the input channel (i.e. input to 130); a current mirror (i.e. 131, fig. 5, see par. [0061]), deployed between the input channel (i.e. Iref input, fig. 5) and the output channel (i.e. Io output) and coupled to the current source (i.e. 110); an output enable switch (i.e. 136, fig. 5), deployed in the output channel (i.e. output channel for Io, fig. 5) and coupled to the current mirror (i.e. 131); and a control circuit (i.e. 130), coupled between the input channel (i.e. Iref input, fig. 5) and the output channel (i.e. output channel for Io, fig. 5), to form a feedback loop through the input channel (i.e. see par. [0063]).
In re to claim 5-8, Kim disclose the current driver (i.e. 100, fig. 1, see par. [0030]) of claim 1, wherein the current source (i.e. 110) is configured to generate a reference current (i.e. Iref) in the input channel (i.e. input to 130, fig. 1); wherein the current mirror (i.e. 131, fig. 5) is configured to generate a driving current (i.e. the driving current to switch 136, fig. 5, see par. [0061]), according to the reference current (i.e. according to Iref, fig. 5); wherein the output enable switch (i.e. 136, fig. 5) is configured to enable an output of the driving current (i.e. Itrim); wherein the output enable switch comprises a high-voltage transistor (i.e. 136 is a MOSFET capable of high voltage, see fig. 5 and par. [0063]).
In re to claims 9-11, Kim disclose the current driver (i.e. 100, fig. 1, see par. [0030]) of claim 1, wherein the current mirror (i.e. 131, fig. 5) comprises: a first transistor (i.e. 133, fig. 5), deployed in the input channel (i.e. the Iref input channel, fig. 5); and a second transistor (i.e. 134, fig. 5), deployed in the output channel (i.e. the Io output channel, see fig. 5); further comprising: an input control transistor (i.e. 135, fig. 5), deployed in the input channel (i.e. the Iref input channel, fig. 5) and coupled between the current source (i.e. 110, see fig. 1) and the current mirror (i.e. 131, fig. 5); and a bias generator (i.e. VB, 135, 137, fig. 5), coupled to the input control transistor (i.e. 135, fig. 5, see par. [0061]); wherein the bias generator is configured to supply a reference voltage (i.e. Vx) to the input control transistor (i.e. 135, fig. 4, see par. [0060-0063]).
In re to claim 14, Kim disclose the current driver (i.e. 100, fig. 1, see par. [0030]) of claim 1, wherein the control circuit (i.e. 130), comprises an operational amplifier (i.e. 137).
In re to claim 16, Kim disclose a current driver (i.e. 100, fig. 1, see par. [0030]) having an input channel (i.e. the channel of Iref) and an output channel (i.e. the channel of Io), comprising: a current source (i.e. 110), deployed in the input channel (i.e. input to 130) and coupled to the current source (i.e. 110, fig. 1); a current mirror (i.e. 131, fig. 5, see par. [0061]), deployed between the input channel (i.e. Iref input, fig. 5) and the output channel (i.e. Io output) and coupled to the input control transistor (i.e. 135, fig. 5); an output enable switch (i.e. 136, fig. 5), deployed in the output channel (i.e. output channel for Io, fig. 5) and coupled to the current mirror (i.e. 131); and a first operational amplifier (i.e. 137, fig. 5), comprising: a first input terminal (i.e. the inverting input of 137), coupled to the output channel (i.e. CH, fig. 5); a second input terminal (i.e. the n0n-inverting input of 137), coupled to the input channel (i.e. the Iref channel, fig. 5); and an output terminal (i.e. CH), coupled to the input control transistor (i.e. 135, fig. 5).
In re to claim 20-23, Kim disclose the current driver (i.e. 100, fig. 1, see par. [0030]) of claim 16, wherein the current source (i.e. 110) is configured to generate a reference current (i.e. Iref) in the input channel (i.e. input to 130, fig. 1); wherein the current mirror (i.e. 131, fig. 5) is configured to generate a driving current (i.e. the driving current to switch 136, fig. 5, see par. [0061]), according to the reference current (i.e. according to Iref, fig. 5); wherein the output enable switch (i.e. 136, fig. 5) is configured to enable an output of the driving current (i.e. Itrim); wherein the output enable switch comprises a high-voltage transistor (i.e. 136 is a MOSFET capable of high voltage, see fig. 5 and par. [0063]).
In re to claims 24-26, Kim disclose the current driver (i.e. 100, fig. 1, see par. [0030]) of claim 16, wherein the current mirror (i.e. 131, fig. 5) comprises: a first transistor (i.e. 133, fig. 5), deployed in the input channel (i.e. the Iref input channel, fig. 5); and a second transistor (i.e. 134, fig. 5), deployed in the output channel (i.e. the Io output channel, see fig. 5); further comprising: a bias generator (i.e. VB, fig. 5), coupled to the input control transistor (i.e. 137, fig. 5); wherein the bias generator is configured to supply a reference voltage to the input control transistor (i.e. to 137, fig. 5, see pars. [0061-0063]).
Allowable Subject Matter
Claims 2-4, 12, 13, 15, 17-19 and 27-30 are objected to as being dependent upon a
rejected base claims but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In re to claims 2, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the control circuit is configured to control a first voltage
In re to claim 12, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the bias generator, comprises: an operational amplifier comprising: a first input terminal coupled to the input control transistor; a second input terminal, coupled to a reference voltage source; and an output terminal, coupled to the current mirror”.
In re to claim 15, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the operational amplifier comprises: a first input terminal, coupled to the output channel ; a second input terminal, coupled to the input channel; and an output terminal, coupled to the input channel”.
In re to claim 17, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the first operational amplifier is configured to control a first voltage of the input channel to track a second voltage of the output channel”.
In re to claim 27, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the bias generator comprises: a second operational amplifier, comprising: a first input terminal, coupled to the input control transistor; a second input terminal, coupled to a reference voltage source; and an output terminal, coupled to the current mirror”.
In re to claim 29, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the output terminal of the first operational amplifier is coupled to a gate terminal of the input control transistor”.
In re to claim 30, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the first operational amplifier forms a feedback loop through the input channel”.
The art of record does not disclose the above limitations, nor would it be obvious to modify the art of record to include either of the above limitations.
In re to claims 3-4, claims 4 depend on claim 2, thus is also objected for the same reasons provided above.
In re to claim 13, claim 13 depend on claim 12, thus is also objected for the same reasons provided above.
In re to claims 18-19, claims 18-19 depend on claim 17, thus are also objected for the same reasons provided above.
In re to claim 28, claims 28 depend on claim 27, thus are also objected for the same reasons provided above.
Remarks
The examiner has cited columns, line numbers, paragraph numbers, references, or
figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YEMANE MEHARI whose telephone number is (571)270-7603. The examiner can normally be reached M-F 9AM TO 6 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 5712701276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YEMANE MEHARI/Primary Examiner, Art Unit 2838
Prosecution Insights