DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/29/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Petronius et al. (US. Pub: 2017/0314763 A1~hereinafter “Petronius”).
Regarding claim 1, Petronius discloses (in at least figs. 1-4) an optoelectronic assembly, comprising: a substrate (60, 82), which is contiguous and having a cavity formed in the substrate (see figs. 3 and 4); an optoelectronic device ([0030]), which is disposed over the cavity and comprises an array of multiple emitters (84; [0050]; see fig. 11) configured to emit a predefined number of light beams in response to receiving one or more electrical signals; and an integrated circuit (IC) ([0032]-[0036]), which is mounted within the cavity (see fig. 1), between the substrate and the optoelectronic device, and is configured to drive the one or more electrical signals to the optoelectronic device (see fig. 1).
Petronius does not expressly disclose the details of the IC, where the IC: (i) is unpackaged and comprises analog and digital transistors configured to regulate a level of driving current applied to the optoelectronic device, and (ii) comprises a capacitor configured to accumulate current and to deliver driving pulses to the optoelectronic device; and a pi filter, which is electrically connected to a power supply line of the IC and is configured to suppress switching noise having a frequency above 1 GHz on the power supply line.
However, it is well-known in the art to form unpackaged IC driver comprises analog and digital transistors configured to regulate a level of driving current applied to the optoelectronic device, and (ii) comprises a capacitor configured to accumulate current and to deliver driving pulses to the optoelectronic device; and a pi filter, which is electrically connected to a power supply line of the IC and is configured to suppress switching noise having a frequency above 1 GHz on the power supply line as evident by Galvano et al. (US. Pub: 2018/0278011 A1~hereinafter “Galvano”); Chen (US. Pub: 2007/0138971 A1) and Dolganov et al. (US. Pub: 2023/00466942 A1~hereinafter “Dolganov”) of record.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to consider using the analog and digital transistors of Galvano, Chen and Dolganov in the IC driver of Petronius to regulate a level of driving current applied to the optoelectronic device, the capacitor to accumulate current and to deliver driving pulses to the optoelectronic device, and the pi filter, which is electrically connected to a power supply line of the IC to suppress switching noise having a frequency above 1 GHz on the power supply line.
Regarding claim 2, Petronius discloses (in at least figs. 1-4) comprising electrically conductive bumps (46; [0036]), which are disposed between the IC and the optoelectronic device, and are configured to conduct the one or more electrical signals.
Regarding claim 3, Petronius discloses (in at least figs. 1-4) a lens assembly (34, 36) mounted over the optoelectronic device and configured to direct a given number of light beams to a scene opposite the lens assembly (see at least fig. 1), wherein the given number equals the predefined number of the light beams emitted from the optoelectronic device (see at least fig. 1).
Regarding claim 4, Petronius discloses (in at least figs. 1-4) a housing (best seen in at least figs. 1, 3 and 4), which is mounted over the substrate and is configured to shield at least the optoelectronic device and the IC from electromagnetic interference (EMI) (see figs. 1, 3 and 4), wherein at least a portion of the lens assembly extends out of the housing (see at least figs. 1, 3 and 4).
Regarding claim 5, Petronius discloses (in at least figs. 1-4; [0030]) the optoelectronic assembly is mounted on a handheld device and configured to direct the given number of light beams to the scene for producing a three- dimensional (3D) image of the scene, wherein the 3D image has a field-of-view (FOV) orthogonal to an axis, which is directed at an acute angle relative to a plain of a chassis of the handheld device.
Claim(s) 6-7 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Petronius et al. (US. Pub: 2017/0314763 A1~hereinafter “Petronius”) of record in view of Allouche et al. (US. Pub: 2020/0185875 A1~ hereinafter “Allouche”) of record.
Regarding claim 6, Petronius discloses all the claimed limitations except for a filler, which is disposed between an edge of the IC and the cavity, and surrounds the edge of the IC, the filler is configured to protect the IC from light radiation impinging on at least the edge of the IC.
Allouche in the same field of endeavor discloses (in at least figs. 3 and 4; [0045]; [0048]) a filler, which is disposed between an edge of the IC and the cavity, and surrounds the edge of the IC, the filler is configured to protect the IC from light radiation impinging on at least the edge of the IC and to provide additional thermal dissipation with respect to the heat generated at the backside of the VCSEL ([0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the optoelectronic assembly device of Petronius with the filler teaching of Allouche in order to protect the IC from light radiation impinging on at least the edge of the IC and to provide additional thermal dissipation with respect to the heat generated at the backside of the VCSEL.
Regarding claim 7, Petronius discloses (in at least figs. 1-4) the light radiation comprises a portion of the light beams reflected from one or both of the lens assembly and the housing (see at least fig. 1), but is silent about the filler comprises resin configured to attenuate at least a predefined wavelength of the reflected light beams.
Allouche discloses (in at least figs. 3 and 4; [0045]) a filler, which is disposed between an edge of the IC and the cavity, and surrounds the edge of the IC, the filler is configured to protect the IC from light radiation impinging on at least the edge of the IC and to provide additional thermal dissipation with respect to the heat generated at the backside of the VCSEL ([0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to consider using a resin material in the filler material of Allouche in order to attenuate at least a predefined wavelength of the reflected light beams, since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination. Dolganov et al. (US. Pub: 2023/0046942 A1) of record discloses a filler comprises resin ([0020]-[0021]).
Regarding claim 26, Petronius as modified by Allouche does not expressly disclose the IC is disposed within the cavity such that a first upper surface of the IC is flush with a second upper surface of the substrate.
However, both Petronius and Allouche disclose (in at least [0032]-[0036] Petronius; [0020]; [0023] Allouche) the IC is disposed within the cavity.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to arrange the IC of Petronius as modified by Allouche such that a first upper surface of the IC is flush with a second upper surface of the substrate, since it has been held that rearranging parts of an invention involves only routine skill in the art.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-7 and 26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELMITO BREVAL whose telephone number is (571)270-3099. The examiner can normally be reached M-Th~ 7:30-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James R. Greece can be reached at 571-272-3711. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
ELMITO BREVAL
Primary Examiner
Art Unit 2875
/ELMITO BREVAL/Primary Examiner, Art Unit 2875
Prosecution Insights