Detailed Action
The instant application having Application No. 18/830949 has a total of 10 claims pending in the application; there are 2 independent claims and 8 dependent claims, all of which are ready for examination by the examiner. This Office action is in response to the claims filed 9/11/24 Claims 1-10 are pending.
NOTICE OF PRE-AIA OR AIA STATUS
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant's drawings submitted 9/11/24 are acceptable for examination purposes.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over McIlroy et al. (U.S. Patent Application Publication No. 2020/0249877), herein referred to as McIlroy et al., in view of Liu (U.S. Patent Application Publication No. 2006/0085737), herein referred to as Liu.
Referring to claim 1, McIlroy et al. disclose as claimed, a storage system comprising: a controller including a processor and a data compression/decompression circuit (see fig. 1, showing a storage system and see fig. 6, showing a compression management component as part of a storage system, which contains a processor), wherein the controller performs in-line compression of data from a host and post-process compression of in-line compressed data stored in one or more storage drives (see para. 25, where the CMC can perform inline compression and/or post-process compression of the in-line data and write the data to a memory component. See para. 33, where the memory component can be a disk. See fig. 11 and fig. 12, where requests can come from clients or different computer systems), the in-line compression includes: generating in-line compressed data by executing a compression process including first dictionary compression on the data from the host using the data compression/decompression circuit; and storing the in-line compressed data in the one or more storage drives (see para. 25, where the CMC may manage inline compression of data as it is being written to memory and see para. 82-87, regarding several different compression algorithm options, many of which include dictionary compression, such as LZMA or LZO), and the post-process compression includes: generating the data by decompressing the in-line compressed data read from the one or more storage drives using the data compression/decompression circuit (see para. 47, where when generating post-process compression data, the in-line compressed data is read and decompressed first); and generating post-process compressed data by executing a compression process including second dictionary compression on the data using the processor, and storing the post-process compressed data in the one or more storage drives (see para. 25, where the CMC may manage post-process compression of data as it is being written to memory and see para. 82-87, regarding several different compression algorithm options, many of which include dictionary compression, such as LZMA or LZO. Therefore a second dictionary compression algorithm may be selected for the post-process compression).
McIlroy et al. disclose the claimed invention except for where the data is plaintext data; and the second dictionary compression being more excellent in character string search capability than the first dictionary compression,
However, Liu discloses wherein the data is plaintext data (see para. 2-8, where XML documents are compressed. XML is a plaintext data format); and the second dictionary compression being more excellent in character string search capability than the first dictionary compression (see para. 92-93, where multiple dictionaries may be used for compression, and some are better for reducing the string search time and may speed up compression).
McIlroy et al. and Liu are analogous art because they are from the same field of endeavor of data compression (see McIlroy et al., abstract and Liu, abstract, regarding data compression).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify McIlroy et al. to comprise wherein the data is plaintext data; and the second dictionary compression being more excellent in character string search capability than the first dictionary compression, as taught by Liu, in order to speed up compression and search time (see Liu, para. 93).
Claim 10 recites similar limitations to claim 1 and would be rejected using the same rationale.
As to claim 7, McIlroy et al. and Liu also disclose the storage system according to claim 1, wherein an upper limit of at least one of the number of hash bits and the number of entries in a hash table for the second dictionary compression is larger than that in a hash table for the first dictionary compression, and/or the number of characters of a character string in the hash table for the second dictionary compression is smaller than that in the hash table for the first dictionary compression (see McIlroy et al., para. 82-91, regarding various compression formats possible such as LZMA, LZO or LZ4. Formats such as LZMA use a larger dictionary size, of up to 4GB and would therefore need more hash entries for compression and would be larger than a format with a smaller dictionary such as LZ4, which has a dictionary size of 64kb).
Claims 2-4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over McIlroy et al. and Liu and in view of Mizushima et al. (U.S. Patent Application Publication No. 2022/0188030), herein referred to as Mizushima et al.
As to claim 2, McIlroy et al. and Liu disclose the claimed invention except for the storage system according to claim 1, wherein the compression process performed by the data compression/decompression circuit includes encoding different from the first dictionary compression using a first compression/decompression algorithm after the first dictionary compression is executed, and in the post-process compression, after the processor compresses the plaintext data by the second dictionary compression, the post-process compressed data is generated by executing encoding using the first compression/decompression algorithm.
However, Mizushima et al. disclose wherein the compression process performed by the data compression/decompression circuit includes encoding different from the first dictionary compression using a first compression/decompression algorithm after the first dictionary compression is executed, and in the post-process compression, after the processor compresses the plaintext data by the second dictionary compression, the post-process compressed data is generated by executing encoding using the first compression/decompression algorithm (see para. 8-10, where dictionary compression may be combined with a code called a range code. See para. 40, where range coding processing takes place after the dictionary compression in LZMA for example, which McIlroy et al. already teaches. See fig. 2a, showing the encoding being executed after the dictionary compression. See para. 84, where the range coding processing is performed by compression/decompression circuit that is also doing the dictionary compression).
McIlroy et al. and Mizushima et al. are analogous art because they are from the same field of endeavor of data compression (see McIlroy et al., abstract and Mizushima et al., abstract, regarding data compression).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify McIlroy et al. to comprise wherein the compression process performed by the data compression/decompression circuit includes encoding different from the first dictionary compression using a first compression/decompression algorithm after the first dictionary compression is executed, and in the post-process compression, after the processor compresses the plaintext data by the second dictionary compression, the post-process compressed data is generated by executing encoding using the first compression/decompression algorithm, as taught by Mizushima et al., in order to improve the performance of a dictionary based compression algorithm (see Mizushima et al., para. 8-10).
As to claim 3, McIlroy et al., Liu and Mizushima et al. also disclose the storage system according to claim 2, wherein in the post-process compression, the encoding is executed by the processor using the first compression/decompression algorithm (see Mizushima et al., fig. 1, where the storage controller does compression/decompression. See fig. 2a, showing dictionary compression followed by range coding, and see para. 84, where the compression/decompression circuit also performs the range coding processing).
As to claim 4, McIlroy et al., Liu and Mizushima et al. also disclose the storage system according to claim 2, wherein in the post-process compression, the encoding is executed using the first compression/decompression algorithm by inputting the data compressed by the second dictionary compression to the data compression/decompression circuit (see Mizushima et al., fig. 2a, showing dictionary compression followed by range coding, therefore range encoding would be executed by inputting the data compressed by the second dictionary compression).
As to claim 9, McIlroy et al., Liu and Mizushima et al. also disclose also disclose the storage system according to claim 2, wherein the controller reads the data compressed by the post-process compression from the one or more storage drives, decompresses the compressed data into the plaintext data by the data compression/decompression circuit, and transmits the decompressed data to the host (see McIlroy et al., para. 36, where the CMC can read portions of a file and decompress that desired portion. Also see para. 94, where reads requests may be satisfied by an L2 cache, but it is desirable to decompress the data and add it to the L1 cache. See fig. 12, where read/write requests from a client-server or host would be fulfilled, and therefore the decompressed data would be sent back to the host).
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over McIlroy et al. and Liu and in view of Natu et al. (U.S. Patent Application Publication No. 2024/0192869), herein referred to as Natu et al.
As to claim 5, McIlroy et al. and Liu disclose the claimed invention except for the storage system according to claim 1, wherein the controller starts the post-process compression when an operating rate of the processor is lower than a preset threshold.
However, Natu et al. disclose wherein the controller starts the post-process compression when an operating rate of the processor is lower than a preset threshold (see para. 79 and 93, where background operations such as compression may be performed during free or idle periods. A free or idle period may be measured by LLR or IOPS metric. Para. 92 states that background operations can be postponed during peaks, bursts or increases, and therefore the compression would take place when the operating rate of the processor is lower than a peak).
McIlroy et al. and Natu et al. are analogous art because they are from the same field of endeavor of data storage systems (see McIlroy et al., abstract and Natu et al., abstract, regarding data storage systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify McIlroy et al. to comprise wherein the controller starts the post-process compression when an operating rate of the processor is lower than a preset threshold., as taught by Natu et al., in order to allow the processor to have a higher peak speed of processing without being slowed down by compression operations that could instead be performed during an idle or slower time period.
As to claim 13, McIlroy et al. and Liu disclose the claimed invention except for the storage system according to claim 1, wherein the controller executes the post-process compression during garbage collection in the one or more storage drives.
However, Natu et al. disclose wherein the controller executes the post-process compression during garbage collection in the one or more storage drives (see para. 79 and 93, where background operations may be performed during free or idle periods. Therefore, as compression and garbage collection are both background operations as stated in para. 79 and 93, they would be performed at the same time during free/idle periods).
McIlroy et al. and Natu et al. are analogous art because they are from the same field of endeavor of data storage systems (see McIlroy et al., abstract and Liu, abstract, regarding data storage systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify McIlroy et al. to comprise wherein the controller executes the post-process compression during garbage collection in the one or more storage drives, as taught by Natu et al., in order to allow the processor to have a higher peak speed of processing without being slowed down by compression or garbage collection operations that could instead be performed during an idle or slower time period.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over McIlroy et al. and Liu and in view of Armangau et al. (U.S. Patent No. 11,068,405), herein referred to as Armangau et al.
As to claim 6, McIlroy et al. and Liu disclose the claimed invention except for the storage system according to claim 1, wherein in the post-process compression, the oldest data is selected from among candidate data stored in the one or more storage drives.
However, Armangau et al. disclose wherein in the post-process compression, the oldest data is selected from among candidate data stored in the one or more storage drives (see col. 7, lines 35-67 and col. 11, lines 14-20, where a set of the oldest blocks of data are selected as an aggregation set to be compressed and then stored in non-volatile storage).
McIlroy et al. and Armangau et al. are analogous art because they are from the same field of endeavor of data storage systems (see McIlroy et al., abstract and Armangau et al., abstract, regarding data storage systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify McIlroy et al. to comprise wherein in the post-process compression, the oldest data is selected from among candidate data stored in the one or more storage drives, as taught by Armangau et al., in order to select data that would be modified less often and therefore require overall less compression and processor cycles to keep data compressed, which would increase a system’s bandwidth and speed for other tasks.
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-10 have received a first action on the merits and are the subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
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/A.O/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132