DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Drogi et al. (USP 11,239,800).
Regarding claim 1, Drogi et al.’s figure 6A shows a transmission chain (figure 11) comprising: a power amplifier stage (25) comprising a signal input (RFin), a voltage supply input (VCC_PA), and at least one bias input (bias1 and bias2) distinct and different from the voltage supply input; and a bias circuit (101, 52, 22) coupled to the power amplifier stage, the bias circuit comprising: a bias signal output (bias1 and bias2) coupled to the at least one bias input of the power amplifier stage and configured to provide at least one bias signal to the power amplifier stage; a first power supply input configured to be coupled to a first power supply that provides a first voltage level (one of the output from 102); a second power supply input configured to be coupled to a second power supply that provides a second voltage level (another output from the circuit 102) ;a switching circuit (103, 104, 105) selectively switching between the first power supply input and the second power supply input; and a float circuit (filter circuit 52) configured to smooth a transition between the first voltage level and the second voltage level when the switching circuit switches between the first power supply input and the second power supply input as called for in claim 1.
Regarding claim 2, Drogi et al. discloses that the power amplifier stage comprises a plurality of field-effect transistors (FETs) and the bias circuit further is coupled to each of the plurality of FETs at a respective gate (column 15, lines 60-64).
Regarding claim 3, , Drogi et al. discloses wherein the switching circuit is configured to switch between the first power supply input and the second power supply input based on fluctuations in difference between the first voltage level and the second voltage level (envelope tracker).
Regarding claim 4, , Drogi et al. discloses a current source (223 or 224 provides a current source, figure 8C) coupled to the first power supply input via circuit 21.
Regarding claim 5, the bias circuit is configured to provide equal bias signals to each of the plurality of FETs (bias1 and bias2 are assumed to be equal otherwise would have stated differently).
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wagh et al. (USP 9,843,293).
Regarding claim 1, Wagh et al.’s figure 8 shows a transmission chain comprising: a power amplifier stage (M1-M4) comprising a signal input (RFin), a voltage supply input (VCC), and at least one bias input (gate electrodes of transistors M1-M4) distinct and different from the voltage supply input (VCC); and a bias circuit (R1-R4, M10, R81-R84, M81, 815) coupled to the power amplifier stage, the bias circuit comprising: a bias signal output (outputs from 315) coupled to the at least one bias input of the power amplifier stage and configured to provide at least one bias signal to the power amplifier stage; a first power supply input configured to be coupled to a first power supply that provides a first voltage level (VB4/VB3/VB2); a second power supply input configured to be coupled to a second power supply that provides a second voltage level (V’B4/V’B3/V’B2) ; a switching circuit (315) selectively switching between the first power supply input and the second power supply input; and a float circuit (RC filter circuits R12-R14; C2-C4) configured to smooth a transition between the first voltage level and the second voltage level when the switching circuit switches between the first power supply input and the second power supply input as called for in claim 1.
Regarding claim 2, Wagh et al. discloses that the power amplifier stage comprises a plurality of field-effect transistors (FETs) and the bias circuit further is coupled to each of the plurality of FETs at a respective gate.
Regarding claim 3, , Wagh et al. discloses wherein the switching circuit is configured to switch between the first power supply input and the second power supply input based on fluctuations in difference between the first voltage level and the second voltage level.
Regarding claim 4, , Wagh et al. discloses a current source (combination of M81 and 815) provides a current source coupled to the first power supply input (R81-R84).
Regarding claim 6, wherein the bias circuit is configured to provide bias signals that are piecewise linear functions of an input voltage (voltages divider R1-R4; R81-R82).
Regarding claim 7, the piecewise linear functions are configured to avoid FET turn off at low input voltages.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Drogi et al. (USP 11,239,800) in view of Peng (US 2022/0385241).
Regarding claim 8, Drogi et al. reference discloses a transmitter chain comprising all the aspects of the present invention as noted above except the bias circuit is further configured to receive information from a temperature sensor as called for in claim 8.
Peng’s figure 8 show a bias circuit for biasing a power amplifier (T1) and further receiving information from a temperature sensor (12) for regulating the bias voltage. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include Peng’s temperature sensor in Drogi et al.’s circuit arrangement for the purpose of an accurate bias voltage as taught by Peng reference.
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Drogi et al. (USP 11,239,800) in view of Scott et al. (US 2023/0096011).
Regarding claim 9, Drogi et al. reference discloses a transmitter chain comprising all the aspects of the present invention as noted above except the bias circuit is further configured to receive information from an over current protection circuit as called for in claim 9.
Scott et al.’s figure 6 shows a power amplifier with a bias circuit receiving information from a current protection circuit (220). Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include Scott et al.’s over current protection circuit in Drogi et al.’s circuit arrangement for the purpose of reducing/eliminating over current scenario as taught by Scott et al. reference (see paragraph 0069).
Regarding claims 10-11, Drogi et al. reference discloses a transmitter chain comprising all the aspects of the present invention as noted above except the bias circuit is further configured to receive information from an over voltage protection circuit; the bias circuit is configured to prioritize information from the over voltage protection circuit over information relating to the first power supply and the second power supply as called for in claims 10-11.
Scott et al.’s figure 6 shows a power amplifier with a bias circuit receiving information from an overvoltage protection circuit in relation to the power supply (226). Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include Scott et al.’s over voltage protection circuit in Drogi et al.’s circuit arrangement for the purpose of reducing/eliminating over voltage scenario as taught by Scott et al. reference (see paragraph 0069).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Wagh et al. (USP 9,843,293) in view of Peng (US 2022/0385241).
Regarding claim 8, Wagh et al. reference discloses a transmitter chain comprising all the aspects of the present invention as noted above except the bias circuit is further configured to receive information from a temperature sensor as called for in claim 8.
Peng’s figure 8 show a bias circuit for biasing a power amplifier (T1) and further receiving information from a temperature sensor (12) for regulating the bias voltage. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include Peng’s temperature sensor in Wagh et al.’s circuit arrangement for the purpose of an accurate bias voltage as taught by Peng reference.
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wagh et al. (USP 9,843,293) in view of Scott et al. (US 2023/0096011).
Regarding claim 9, Wagh et al. reference discloses a transmitter chain comprising all the aspects of the present invention as noted above except the bias circuit is further configured to receive information from an over current protection circuit as called for in claim 9.
Scott et al.’s figure 6 shows a power amplifier with a bias circuit receiving information from a current protection circuit (220). Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include Scott et al.’s over current protection circuit in Wagh et al.’s circuit arrangement for the purpose of reducing/eliminating over current scenario as taught by Scott et al. reference (see paragraph 0069).
Regarding claims 10-11, Wagh et al. reference discloses a transmitter chain comprising all the aspects of the present invention as noted above except the bias circuit is further configured to receive information from an over voltage protection circuit; the bias circuit is configured to prioritize information from the over voltage protection circuit over information relating to the first power supply and the second power supply as called for in claims 10-11.
Scott et al.’s figure 6 shows a power amplifier with a bias circuit receiving information from an overvoltage protection circuit in relation to the power supply (226). Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include Scott et al.’s over voltage protection circuit in Wagh et al.’s circuit arrangement for the purpose of reducing/eliminating over voltage scenario as taught by Scott et al. reference (see paragraph 0069).
Allowable Subject Matter
Claims 12-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: over Drogi et al. (USP 11,239,800) and Wagh et al. (USP 9,843,293), prior art of record fails to teach or fairly suggest an over power protection signal input configured to receive a signal that causes the bias circuit to debias the power amplifier stage; and a predistortion signal input configured to cause the bias circuit to apply a predistortion bias to the power amplifier stage; and wherein the bias circuit is configured to disable the predistortion bias when the signal indicates an over power condition is occurring as called for in claim 12. Claims 13-18 depend on claim 12.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In this regard, applicant’s cited prior art has been carefully considered.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN THIEU LAM whose telephone number is (571)272-1744. The examiner can normally be reached Monday-Friday, 8:30 am to 5:00 pm.
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/TUAN T LAM/Primary Examiner, Art Unit 2836 7/21/2026
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