Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed August 5, 2026 is acknowledged. Claims 16-20 drawn to the non-elected invention(s) have been withdrawn from examination for patentability.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 8 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. In claim 8, the term “the at least one middle cascode transistor” lacks proper antecedent basis.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-5, and 7 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2021/0091726 to Esmael.
With respect to claim 1, Esmael discloses in Fig. 4 a power amplification circuit (e.g., 400) comprising:
an amplifier circuit (e.g., 110) comprising a plurality of cascode transistors coupled in a series between an output node (e.g., 104) and a reference voltage node, the series comprising a last cascode transistor (e.g., 202) coupled to the reference voltage node and determining a current in the output node (e.g., 104);
a protection circuit (e.g., 120) configured to generate a feedback signal (e.g., Vbias2) in response to an output voltage (e.g., Vdn) on the output node (e.g., 104) exceeding a threshold (e.g., per Paras. 67-68, “as the voltage sensed by the sensing circuit 122 increases, … the second DC voltage” supplied to the control terminal 206 of transistor 202 increases to thereby reduce the voltage difference between the terminals of the transistor 202 and protect 202, wherein the voltage difference between terminals 204 and 206 of 202 does not exceed a threshold corresponding to the breakdown operating condition of 202; here, whenever there is any voltage change at 104 to be above a previous voltage at 104 that leads to an increased Vibas2 to protect 202, the previous voltage at 104 is considered to be the claimed threshold, and the new, changed Vbias2 in response to the previous voltage at 104 being exceeded is considered to be the claimed feedback signal); and
a bias circuit (e.g., 248) configured to reduce a bias voltage of the last cascode transistor (e.g., 202) based on the feedback signal (e.g., Vbias1) (e.g., depending on whether Vbias increases or decreases, the bias voltage at 206 is increased or reduced).
With respect to claim 2, the plurality of cascode transistors comprises a first cascode transistor (e.g., 102) coupled to the output node (e.g., 104), the last cascode transistor (e.g., 202) coupled to the reference voltage node, and at least one middle cascode transistor (e.g., more transistors between 102 and 208 as indicated by intermittent dashes and per Para. 44) coupled in series between the first cascode transistor and the last cascode transistor.
With respect to claim 4, the plurality of cascode transistors (e.g., 102 and 202) are field-effect transistors (FETs); and the control terminals comprise gates of the FETs.
With respect to claim 5, each of the plurality of cascode transistors (e.g., 102 and 202) are a first type of FET, wherein the first type of FET is an N-channel FET.
With respect to claim 7, having more than 3 middle transistors between 102 and 202 is presumably within the disclosure of Esmael (e.g., Para. 44).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Esmael.
With respect to claim 8, Esmael discloses in Fig. 4 protection circuit 120 and amplifier 110 having middle components indicated by dotted lines. Emael fails to explicitly disclose that the middle transistors in 110 as indicated by dots in Fig. 4 are also protected by the same method protecting the end transistors in 110. However, since Esmael discloses in Fig. 2 protection circuit 120 and amplifier 110 having middle components indicated by dotted lines and protection by 120 is also beneficial to middle transistors in 110 in Fig. 4, it would have been apparent (“common sense”) to a person of ordinary skill in the art to apply the same method protecting the end transistors in 110 in Fig. 4 to the middle transistors of 110 because such a modification provides additional protection.
With respect to claim 9, the protection circuit (e.g., 120) is further coupled to (e.g., via 102) a first source/drain terminal of one of the at least one middle cascode transistors, and the protection circuit (e.g., 120) further generates a second feedback signal (e.g., Vbias for the middle transistors) to the bias circuit to reduce a bias on the control terminal of one of the at least one middle cascode transistor.
Allowable Subject Matter
Claims 3, 6, and 10-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jung KIM whose telephone number is (571)270-7964. The examiner can normally be reached on M-F from 9AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Regis BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUNG KIM/
Primary Examiner, Art Unit 2836
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