DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Foreign priority is not claimed for this application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/14/2024; 12/05/2024; 02/27/2025; 06/25/2025; 09/26/2025; 10/31/2025; 01/31/2026; 05/11/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5, and 13 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 10361744 by Khlat.
Regarding claim 1, Khlat teaches a transmission circuit (Fig. 3, 4) comprising:
a power amplifier circuit (10) configured to amplify a radio frequency (RF) signal (72) from a time-variant input power (Pin) to a time-variant output power (Pout) based on a modulated voltage (Vcc);
an envelope tracking (ET) integrated circuit (ETIC) (tracker circuit), coupled to the power amplifier circuit (10) via a conductive path and configured to generate the modulated voltage (Vcc) based on a modulated target voltage (Vtarget); and
a transceiver circuit (48) comprising:
a signal processing circuit (70) configured to generate the RF signal (72) in the time-variant input power (Pin) based on a time-variant modulation vector (74);
a voltage processing circuit (50) configured to generate a modulated digital target voltage (Vtarget-D) from the time-variant modulation vector (74);
a current processing circuit (54) configured to add a compensation term (∆V ;Col. 7 lines 42-44) to the modulated digital target voltage (Vtarget-D) to thereby generate a modified digital target voltage (V’target-D);and
a digital-to-analog converter DAC (66) configured to convert the modified digital target voltage (V’target-D) into the modulated target voltage (Vtarget; Col. 8 lines 15-20) to thereby cancel a ripple in the modulated voltage (Vcc).
Regarding claim 5, Khlat teaches the transmission circuit (Fig. 3, 4) of claim 1, wherein:
the ripple in the modulated voltage (Vcc) is caused by an interaction between a modulated current (Icc) in the power amplifier circuit (10) and a total inductive impedance (Zsource) collectively presented to the power amplifier circuit (10) by the ETIC (tracker circuit) and the conductive path (connection of tracker circuit to PA)(Col. 9 lines 15-23); and
the current processing circuit (54) is further configured to determine the compensation term (∆V) in accordance with the total inductive impedance (Zsource; Col. 9 lines 42-50).
Regarding claim 13, Khlat teaches a transceiver circuit (Fig. 3, 4 #48) comprising:
a signal processing circuit (70) configured to generate the RF signal (72) in the time-variant input power (Pin) based on a time-variant modulation vector (74);
a voltage processing circuit (50) configured to generate a modulated digital target voltage (Vtarget-D) from the time-variant modulation vector (74);
a current processing circuit (54) configured to add a compensation term (Col. 7 lines 42-44) to the modulated digital target voltage (Vtarget-D) to thereby generate a modified digital target voltage (V’target-D);and
a digital-to-analog converter DAC (66) configured to convert the modified digital target voltage (V’target-D) into the modulated target voltage (Vtarget; Col. 8 lines 15-20).
Allowable Subject Matter
Claims 2-4, 6-12, and 14-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art fails to teach the limitations that are presented in these claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAREH SHAMIRYAN whose telephone number is (703)756-4616. The examiner can normally be reached M-F: 7:00AM-4:00PM PT.
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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