DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first and second film layer structures from claims 3-5, 7-8, 10-12, 16-18, and 20 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 8 is objected to because of the following informalities:
Claim 8 recites “the second polar electrode is located on a surface of the fourth semiconductor layer which faces away from the reflective layer and electrically connected to the second semiconductor layer through the second interlayer via.” This phrasing could cause confusion as to which element is electrically connected to the second semiconductor layer: the second polar electrode or a surface of the fourth semiconductor layer. It is suggested that this be revised to “the second polar electrode is located on a surface of the fourth semiconductor layer which faces away from the reflective layer, and the second polar electrode is electrically connected to the second semiconductor layer through the second interlayer via.”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 11 (and 12) recite “forming the first (second) polar electrode filling the first interlayer via on a surface…” It is unclear exactly what this means, if it is forming the first polar electrode by filling the first interlayer via, forming the first polar electrode which fills the first interlayer via, simply forming it in the via, if the filling part is erroneous and it is just formed on a surface of the third semiconductor facing away from the reflective layer, or something else. For the purposes of examination, this was interpreted as forming the first polar electrode in the first interlayer via and on a surface of the third semiconductor layer which faces away from the reflective layer.
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Zhang figures 4 and 5 above; Hwang figures 9 and 10 below.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (CN 102593109 A), hereinafter referred to as "Zhang", in view of Hwang (KR 20130027302 A), hereinafter referred to as "Hwang".
Regarding claim 1, Zhang discloses A light-emitting diode chip comprising: a first epitaxial light-emitting structure (102 in Zhang figure 4) comprising a first semiconductor layer (1021 in figure 4), a first light-emitting layer (1022 in figure 4), and a second semiconductor layer (1023 in figure 4) stacked in sequence (1021, 1022m and 1023 are stacked in that order); a second epitaxial light-emitting structure (104 in figure 4) located at a side of an insulating layer which faces away from the first epitaxial light-emitting structure, and comprising a third semiconductor layer (1041 in figure 4), a second light-emitting layer (1042 in figure 4), and a fourth semiconductor layer (1043 in figure 4) that are sequentially stacked (1041, 1042, and 1043 are stacked in that order), wherein the first semiconductor layer and the third semiconductor layer have first polarities (1021 and 1041 are both anodes, see Zhang paragraph 0053 and 0058), and the second semiconductor layer and the fourth semiconductor layer have second polarities (1023 and 1043 are both cathodes, see Zhang paragraph 0055 and 0060); a connection electrically connecting the first semiconductor layer and the third semiconductor layer (See connections in figure 5. The two structures are connected in parallel, [see paragraph 0062] which means there is a connection between both anodes); and a connection electrically connecting the second semiconductor layer and the fourth semiconductor layer (See connections in figure 5. The two structures are connected in parallel, [see paragraph 0062] which means there is a connection between both cathodes).
Zhang does not explicitly disclose a reflective layer, nor does Zhang explicitly state that the connections between the anodes and cathodes of the structures are “polar electrodes” (which is taken here to mean electrodes that connect polar regions).
Hwang teaches a reflective layer at a side of the first epitaxial light-emitting structure (intermediate structure 150 in figures 9 and 10, which can be reflective see Hwang paragraph 0094, specifically layer 153). This layer is in between two light emitting structures, 120 and 130, and thus if placed in the same position in Zhang’s device would have the second epitaxial light emitting structure be located at a side of the reflective layer which faces away from the first epitaxial light-emitting structure. Hwang also teaches that this reflecting layer reduces light loss (Hwang paragraph 0095).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the reflecting layer of Hwang to the device of Zhang in order to reduce light loss.
Regarding the first polar electrode and the second polar electrode, Zhang already discloses that the two anodes are electrically connected, and that the two cathodes are electrically connected. It would be obvious to use some sort of conductive material to connect these, which would serve as the polar electrodes. Furthermore, Hwang teaches electrodes that electrically connect the semiconductor layers of Hwang’s device (142, 144, and 146 in Hwang figure 13).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect the first semiconductor layer with the third semiconductor layer and the second semiconductor layer with the fourth semiconductor layer with polar electrodes, such as those of Hwang, in order to achieve the device described by Zhang.
Regarding claim 2, Zhang in view of Hwang teaches all of the limitations of claim 1. Zhang does not disclose any Bragg reflective layers.
Hwang discloses that the reflective layer 150 comprises a first Bragg reflective layer between the first epitaxial light-emitting structure and the reflective layer (layers 151 and 152 in Hwang figure 10; they can have different refractive indices and act as a Bragg reflector, Hwang paragraph 0094); and a second Bragg reflective layer between the second epitaxial light-emitting structure and the reflective layer (layers 154 [labeled 152 above 153] and 155 in Hwang figure 10; they can have different refractive indices and act as a Bragg reflector, Hwang paragraph 0094). These contribute to the reflective property of the intermediate 150, and therefore have the same benefits described above.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the Bragg reflective layers of Hwang in order to reduce light loss.
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Hwang figures 13 and 18
Regarding claim 3, Zhang in view of Hwang teaches all of the limitations of claim 1. Zhang does not give structural details to any electrodes that connect the semiconductor layers, nor does Zhang explicitly disclose a first and second film layer structure.
Hwang teaches a first film layer structure which is a film layer structure between the first semiconductor layer and the third semiconductor layer (128 in Hwang figure 18. This is a structure made of a thin layer, which meets the limitation of a film layer structure), and a second film layer structure which is a film layer structure between the second semiconductor layer and the fourth semiconductor layer (138 in Hwang figure 18. This is a structure made of a thin layer, which meets the limitation of a film layer structure). Hwang also teaches that these electron limiting layers prevent leakage current (See Hwang paragraph 0151).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the film layers of Hwang in order to prevent leakage current.
Hwang also teaches an electrode structure that comprises a first extension portion extending from a sidewall of the third semiconductor layer along a sidewall of a first film layer structure to the first semiconductor layer (146 and 142 in Hwang figure 13, see paragraph 0056. The longest portion that extends vertically along the sidewall of the device is therefore also on the sidewalls of all of the semiconductor layers and the film layers, if they are positioned as they are in figure 18); Hwang teaches that this connects semiconductor layers together and that the integral structure allows it to be easily formed (Hwang paragraph 0111).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use this type of structure to connect the light emitting structures of Zhang in parallel because it is a known technique used to connect semiconductor layers and allows for easy formation of the connection.
Hwang’s connections connect the first and fourth semiconductor layers together and the second and third semiconductor layers together, however, this is because Hwang’s device is arranged in anti-parallel (Hwang paragraph 0062). In connecting the device in parallel, as for Zhang’s device, this connection would naturally go from the top of the third semiconductor layer and extend down to the first semiconductor.
Regarding the second polar electrode, it would be obvious to use this same structure to connect the second and fourth semiconductor layers, since it would accomplish the same result and have the same benefits as discussed above. In order to connect the second and fourth layers using this method, the electrode would naturally go from the top of the fourth semiconductor layer and extend down to the second semiconductor structure. In doing so, the extension portion (long vertical section similar to the 146 to 142 connection in Hwang figure 13) would extend from a sidewall of the fourth semiconductor layer along a sidewall of a second film layer structure (138 in Hwang figure 18) to the second semiconductor layer.
Regarding claim 4, Zhang in view of Hwang teaches all of the limitations of claim 3. The electrode structure of the combined device further shows that the sidewall of the third semiconductor layer, a sidewall of the first film layer structure, and a sidewall of the first semiconductor layer are connected together to form a first step structure (Hwang figure 13), a step surface of the first step structure is the first semiconductor layer (Hwang figure 13. See cut portion of 122 that connects with 142), and the first extension portion extends from the sidewall of the third semiconductor layer along the sidewall of the first film layer structure to the step surface of the first step structure (The longest portion that extends vertically along the sidewall of the device is therefore on the sidewalls of the third semiconductor layer and the film layer, if the film layer 128 is positioned as it is in figure 18).
Regarding claim 5, Zhang in view of Hwang teaches all of the limitations of claim 3. The second electrode structure of the combined device further shows that the sidewall of the fourth semiconductor layer, a sidewall of the second film layer structure, and a sidewall of the second semiconductor layer are connected together to form a second step structure (In order to connect the second and fourth electrodes, the structure would look like the 142 – 146 connection in Hwang figure 13, except stopping at a cut portion of the second semiconductor layer [126]), a step surface of the second step structure is the second semiconductor layer (cut portion of 122 would be in 126 to connect to the second semiconductor layer), and the second extension portion extends from the sidewall of the fourth semiconductor layer to the step surface of the second step structure along the sidewall of the second film layer structure (The longest portion extends vertically along the sidewall of the device particularly the sidewalls of the fourth semiconductor layer and the film layer, if the film layer is positioned as it is in figure 18).
Regarding claim 6, Zhang in view of Hwang teaches all of the limitations of claim 3. The electrode structure of the combined device further shows that the first polar electrode further comprises a first contact portion connected to the first extension portion and in contact with a surface of the third semiconductor layer which faces away from the reflective layer (portion of the electrode on top of the fourth semiconductor layer in Hwang figure 13 that connects to the long vertical portion. For the first electrode which connects the first and third semiconductor layers, this would be on top of the third semiconductor layer); the second polar electrode further comprises a second contact portion connected to the second extension portion and in contact with a surface of the fourth semiconductor layer which faces away from the reflective layer (portion of the electrode on top of the fourth semiconductor layer in Hwang figure 13 that connects to the long vertical portion. For the second electrode which connects the second and fourth semiconductor layers, this would be on top of the fourth semiconductor layer, like in figure 13).
Regarding claim 7, Zhang in view of Hwang teaches all of the limitations of claim 3. Hwang further teaches a first insulating layer that is located between the first extension portion and the first film layer structure and electrically isolates the first extension portion from the first film layer structure (148 in Hwang figure 13. Hwang paragraph 0110); Hwang teaches that this prevents unnecessary short-circuits.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the insulating layer from Hwang in order to prevent unnecessary short-circuits.
As the two electrodes of the combined have the same essential structure, it would be obvious to add a similar insulating layer between the second electrode and the device stack as well for the same reason of preventing unnecessary short-circuits. Thus, the combined device shows a second insulating layer that is located between the second extension portion and the second film layer structure, and that electrically isolates the second extension portion from the second film layer structure.
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Hwang ‘785 figure 21
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Hwang as applied to claim 1 above, and further in view of Hwang (US 20130056785 A1), hereinafter referred to as "Hwang '785".
Regarding claim 8, Zhang in view of Hwang teaches all of the limitations of claim 1. Zhang does not give structural details to any electrodes that connect the semiconductor layers, nor does Zhang explicitly disclose a first and second film layer structure.
Hwang teaches a first film layer structure which is a film layer structure between the first semiconductor layer and the third semiconductor layer (128 in Hwang figure 18. This is a structure made of a thin layer, which meets the limitation of a film layer structure), and a second film layer structure which is a film layer structure between the second semiconductor layer and the fourth semiconductor layer (138 in Hwang figure 18. This is a structure made of a thin layer, which meets the limitation of a film layer structure). Hwang also teaches that these electron limiting layers prevent leakage current (See Hwang paragraph 0151).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the film layers of Hwang in order to prevent leakage current.
Hwang ‘785 teaches an interlayer via structure (242 in Hwang ‘785 figure 21 is in a trench that goes from layer 222 to layer 236, which thus acts as a via structure) that extends through a semiconductor layer and connects it with a lower semiconductor layer (It connects semiconductor layer 236 with semiconductor layer 222), while passing through the intermediate layers. Hwang ‘785 thus teaches a known method of connecting two semiconductor layers that has the predictable result of having them be in electrical contact.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect the first and third semiconductor layers of Zhang using the known technique taught by Hwang ‘785.
When connecting the first to the third layer, rather than to the fourth layer, it can be seen that the combined device would have a first interlayer via extending through the third semiconductor layer and a first film layer structure located between the third semiconductor layer and the first semiconductor layer (the first film structure would be placed above the first light emitting layer, as 128 is in Hwang figure 18, and thus the via would also extend through it), wherein the first polar electrode is located on a surface of the third semiconductor layer which faces away from the reflective layer (In Hwang ‘785 figure 21 the top of the electrode sits on top of the fourth semiconductor layer, which would be the third semiconductor layer in the combined device) and electrically connected to the first semiconductor layer through the first interlayer via.
As the second and fourth semiconductor layers are to be connected in Zhang just as the first and third are, it would be obvious to use this same technique to connect those layers together for the same reasons given above.
When connecting the second and fourth layers together with this, it can be seen that the combined device would have a second interlayer via extending through the fourth semiconductor layer and a second film layer structure between the fourth semiconductor layer and the second semiconductor layer (the second film structure would be placed above the first light emitting layer, as 138 is in Hwang figure 18, and thus the via would also extend through it), wherein the second polar electrode is located on a surface of the fourth semiconductor layer which faces away from the reflective layer (See Hwang ‘785 figure 21, the top electrode part is on top of the fourth electrode layer) and electrically connected to the second semiconductor layer through the second interlayer via (In the combined device the via would stop at the second semiconductor layer so as to connect them as in Zhang).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Hwang.
Regarding claim 9, Zhang discloses A manufacturing method of a light-emitting diode chip comprises: forming a light-emitting diode epitaxial wafer comprising a substrate (101 in Zhang figure 4), a first epitaxial light-emitting structure (102 in Zhang figure 4), and a second epitaxial light-emitting structure (104 in figure 4), wherein the first epitaxial light-emitting structure is formed on a side of the substrate (102 is formed on 101) and comprises a first semiconductor layer (1021 in figure 4), a first light-emitting layer (1022 in figure 4) and a second semiconductor layer (1023 in figure 4), and the second epitaxial light-emitting structure is formed on a side of the layer (1041 in figure 4), a second light-emitting layer (1042 in figure 4) and a fourth semiconductor layer (1043 in figure 4), wherein the first semiconductor layer and the third semiconductor layer have first polarities (1021 and 1041 are both anodes, see Zhang paragraph 0053 and 0058) and the second semiconductor layer and the fourth semiconductor layer have second polarities (1023 and 1043 are both cathodes, see Zhang paragraph 0055 and 0060); forming a connection electrically connecting the first semiconductor layer and the third semiconductor layer (See connections in figure 5. The two structures are connected in parallel, [see paragraph 0062] which means there is a connection between both anodes); and forming a second connection electrically connecting the second semiconductor layer and the fourth semiconductor layer (See connections in figure 5. The two structures are connected in parallel, [see paragraph 0062] which means there is a connection between both cathodes).
Zhang does not explicitly disclose forming a reflective layer, nor does Zhang explicitly state that the connections formed between the anodes and cathodes of the structures are “polar electrodes” (which is taken here to mean electrodes that connect polar regions).
Hwang teaches forming a reflective layer at a side of the first epitaxial light-emitting structure (intermediate structure 150 in figures 9 and 10, which can be reflective see Hwang paragraph 0094, specifically layer 153). This layer is in between two light emitting structures, 120 and 130, and thus if placed in the same position in Zhang’s device would be formed on a side of the first epitaxial light-emitting structure which faces away from the substrate (similar location to insulating layer103 in Zhang figure 4). Furthermore, this would have the second epitaxial light emitting structure be located at a side of the reflective layer which faces away from the first epitaxial light-emitting structure. Hwang also teaches that this reflecting layer reduces light loss (Hwang paragraph 0095).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the reflecting layer of Hwang to the device of Zhang in order to reduce light loss.
Regarding the first polar electrode and the second polar electrode, Zhang already discloses that the two anodes are electrically connected, and that the two cathodes are electrically connected. It would be obvious to use some sort of conductive material to connect these, which would serve as the polar electrodes. Furthermore, Hwang teaches electrodes that electrically connect the semiconductor layers of Hwang’s device (142, 144, and 146 in Hwang figure 13).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect the first semiconductor layer with the third semiconductor layer and the second semiconductor layer with the fourth semiconductor layer with polar electrodes, such as those of Hwang, in order to achieve the device described by Zhang.
Regarding claim 10, Zhang in view of Hwang teaches all of the limitations of claim 9. Zhang does not give structural details regarding forming the electrodes that connect the semiconductor layers, nor does Zhang explicitly disclose a first and second film layer structure.
Hwang teaches a first film layer structure which is a film layer structure between the first semiconductor layer and the third semiconductor layer (128 in Hwang figure 18. This is a structure made of a thin layer, which meets the limitation of a film layer structure), and a second film layer structure which is a film layer structure between the second semiconductor layer and the fourth semiconductor layer (138 in Hwang figure 18. This is a structure made of a thin layer, which meets the limitation of a film layer structure). Hwang also teaches that these electron limiting layers prevent leakage current (See Hwang paragraph 0151).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the film layers of Hwang in order to prevent leakage current.
Hwang also teaches forming an electrode structure that comprises forming a first extension portion to obtain the first polar electrode comprising the first extension portion, , wherein the first extension portion extends from a sidewall of the third semiconductor layer along a sidewall of a first film layer structure to the first semiconductor layer (146 and 142 in Hwang figure 13, see paragraph 0056. The longest portion that extends vertically along the sidewall of the device is therefore also on the sidewalls of all of the semiconductor layers and the film layers, if they are positioned as they are in figure 18); Hwang teaches that this connects semiconductor layers together and that the integral structure allows it to be easily formed (Hwang paragraph 0111).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use this type of structure to connect the light emitting structures of Zhang in parallel because it is a known technique used to connect semiconductor layers and allows for easy formation of the connection.
Hwang’s connections connect the first and fourth semiconductor layers together and the second and third semiconductor layers together, however, this is because Hwang’s device is arranged in anti-parallel (Hwang paragraph 0062). In connecting the device in parallel, as for Zhang’s device, this connection would naturally go from the top of the third semiconductor layer and extend down to the first semiconductor.
Regarding the second polar electrode, it would be obvious to use this same method to form the same kind of structure to connect the second and fourth semiconductor layers, since it would accomplish the same result and have the same benefits as discussed above. In order to connect the second and fourth layers using this method, the electrode would naturally go from the top of the fourth semiconductor layer and extend down to the second semiconductor structure. In doing so, the extension portion (long vertical section similar to the 146 to 142 connection in Hwang figure 13) would extend from a sidewall of the fourth semiconductor layer along a sidewall of a second film layer structure (138 in Hwang figure 18) to the second semiconductor layer.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Hwang as applied to claim 9 above, and further in view of Hwang '785.
Regarding claim 11, Zhang in view of Hwang teaches all of the limitations of claim 9. Zhang does not disclose forming an interlayer via, nor a first film structure.
Hwang teaches a first film layer structure which is a film layer structure between the first semiconductor layer and the third semiconductor layer (128 in Hwang figure 18. This is a structure made of a thin layer, which meets the limitation of a film layer structure). Hwang also teaches that this electron limiting layers prevent leakage current (See Hwang paragraph 0151).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the film layer of Hwang in order to prevent leakage current.
Hwang ‘785 teaches a method of forming a connection between two semiconductor layers where before forming the first polar electrode, the manufacturing method comprises: forming a first interlayer via (the trench which 242 in Hwang ‘785 figure 21 is in goes through several internal layers and acts as an interlayer via; the trench must have been made first in order for the electrode 242 to then be disposed in it, Hwang ‘785 paragraph 0243) extending through the third semiconductor layer and a first film layer structure between the third semiconductor layer and the first semiconductor layer (the trench goes through the layer which the electrode will contact, 236 in Hwang ‘785 figure 21 and where the first film layer structure would be above the first light-emitting layer); the forming the first polar electrode comprises: forming the first polar electrode filling the first interlayer via on a surface (see 112b rejection above) of the third semiconductor layer which faces away from the reflective layer (electrode 242 is in the trench structure and electrode 244 is on top of the layer which the structure is contacting). Hwang ‘785 thus teaches a known method of forming a connection between two semiconductor layers that has the predictable result of having them be in electrical contact.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect the first and third semiconductor layers of Zhang using the known technique taught by Hwang ‘785.
Regarding claim 12, Zhang in view of Hwang teaches all of the limitations of claim 9. Zhang in view of Hwang teaches all of the limitations of claim 9. Zhang does not disclose forming an interlayer via, nor a second film structure.
Hwang teaches a second film layer structure which is a film layer structure between the second semiconductor layer and the fourth semiconductor layer (138 in Hwang figure 18. This is a structure made of a thin layer, which meets the limitation of a film layer structure). Hwang also teaches that this electron limiting layers prevent leakage current (See Hwang paragraph 0151).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the film layer of Hwang in order to prevent leakage current.
Hwang ‘785 teaches a method of forming a connection between two semiconductor layers where before forming the second polar electrode, the manufacturing method comprises: forming a second interlayer via (the trench which 242 in Hwang ‘785 figure 21 is in goes through several internal layers and acts as an interlayer via; the trench must have been made first in order for the electrode 242 to then be disposed in it, Hwang ‘785 paragraph 0243) extending through the fourth semiconductor layer and a second film layer structure between the fourth semiconductor layer and the second semiconductor layer (the trench goes through the layer which the electrode will contact, 236 in Hwang ‘785 figure 21 and where the second film layer structure would be above the first light-emitting layer); the forming the second polar electrode comprises: forming the second polar electrode filling the second interlayer via on a surface (see 112b rejection above) of the fourth semiconductor layer which faces away from the reflective layer (electrode 242 is in the trench structure and electrode 244 is on top of the layer which the structure is contacting). Hwang ‘785 thus teaches a known method of forming a connection between two semiconductor layers that has the predictable result of having them be in electrical contact.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect the second and fourth semiconductor layers of Zhang using the known technique taught by Hwang ‘785.
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Chen figure 8
Claims 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Hwang and Chen et al. (US 20210013186 A1), hereinafter referred to as “Chen”.
Regarding claim 13, Zhang discloses Zhang discloses A light-emitting diode chip comprising: a first epitaxial light-emitting structure (102 in Zhang figure 4) comprising a first semiconductor layer (1021 in figure 4), a first light-emitting layer (1022 in figure 4), and a second semiconductor layer (1023 in figure 4) stacked in sequence (1021, 1022m and 1023 are stacked in that order); a second epitaxial light-emitting structure (104 in figure 4) located at a side of an insulating layer which faces away from the first epitaxial light-emitting structure, and comprising a third semiconductor layer (1041 in figure 4), a second light-emitting layer (1042 in figure 4), and a fourth semiconductor layer (1043 in figure 4) that are sequentially stacked (1041, 1042, and 1043 are stacked in that order), wherein the first semiconductor layer and the third semiconductor layer have first polarities (1021 and 1041 are both anodes, see Zhang paragraph 0053 and 0058), and the second semiconductor layer and the fourth semiconductor layer have second polarities (1023 and 1043 are both cathodes, see Zhang paragraph 0055 and 0060); a connection electrically connecting the first semiconductor layer and the third semiconductor layer (See connections in figure 5. The two structures are connected in parallel, [see paragraph 0062] which means there is a connection between both anodes); and a connection electrically connecting the second semiconductor layer and the fourth semiconductor layer (See connections in figure 5. The two structures are connected in parallel, [see paragraph 0062] which means there is a connection between both cathodes).
Zhang does not explicitly disclose a reflective layer, nor does Zhang explicitly state that the connections between the anodes and cathodes of the structures are “polar electrodes” (which is taken here to mean electrodes that connect polar regions). Zhang also does not disclose a driving substrate that is connected to the diode chip.
Hwang teaches a reflective layer at a side of the first epitaxial light-emitting structure (intermediate structure 150 in figures 9 and 10, which can be reflective see Hwang paragraph 0094, specifically layer 153). This layer is in between two light emitting structures, 120 and 130, and thus if placed in the same position in Zhang’s device would have the second epitaxial light emitting structure be located at a side of the reflective layer which faces away from the first epitaxial light-emitting structure. Hwang also teaches that this reflecting layer reduces light loss (Hwang paragraph 0095).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the reflecting layer of Hwang to the device of Zhang in order to reduce light loss.
Regarding the first polar electrode and the second polar electrode, Zhang already discloses that the two anodes are electrically connected, and that the two cathodes are electrically connected. It would be obvious to use some sort of conductive material to connect these, which would serve as the polar electrodes. Furthermore, Hwang teaches electrodes that electrically connect the semiconductor layers of Hwang’s device (142, 144, and 146 in Hwang figure 13).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect the first semiconductor layer with the third semiconductor layer and the second semiconductor layer with the fourth semiconductor layer with polar electrodes, such as those of Hwang, in order to achieve the device described by Zhang.
Chen teaches a driving substrate (Chen figure 8; circuit layer 110 on substrate 102 has driving elements, see Chen paragraph 0032), wherein a light-emitting diode chip is electrically connected to the driving substrate (Chen figure 8. Diode chip LD2 is connected to the thin film transistor TFT of the driving substrate by the lines RL1 and CL1), and the driving substrate is configured to drive the light-emitting diode chip to emit light (Chen paragraph 0031). It is well known that connecting many light-emitting devices to a driving substrate is a way to make a display device, and Chen also teaches that the lighting device 100 may be applied to any electronic product or electronic device that needs a light source or a light emitting component.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the driving substrate of Chen in order to integrate the diode chip taught by Zhang and Hwang into a display device.
Regarding claim 14, Zhang in view of Hwang and Chen teaches all of the limitations of claim 13. Zhang does not disclose a pixel defining layer or bonding electrodes.
Chen teaches a pixel defining layer provided on a side of the driving substrate (106 in Chen figure 8), wherein a side of the pixel defining layer which faces away from the driving substrate is provided with a groove (accommodating hole AH in Chen figure 8), and at least a part of the light-emitting diode chip is located in the groove (light-emitting diode LD2 is in the groove); a first bonding electrode disposed on an inner wall of the groove and electrically connected to the first polar electrode of the light-emitting diode chip (RL1, which is connected to the first electrode ce1); and a second bonding electrode disposed on the inner wall of the groove and electrically connected to the second polar electrode of the light-emitting diode chip (RL2 which is connected to the second electrode ce2). A pixel-defining layer is a common part of a display to have the pixels not interfere with each other, and Chen also teaches that the accommodating hole structure allows the light-emitting diodes to be formed separately and then transferred and fixed on the substrate (Chen paragraph 0037). This would have the benefit of simplifying manufacturing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the pixel defining layer and groove of Chen in order to simplify the manufacturing.
Regarding claim 15, , Zhang in view of Hwang and Chen teaches all of the limitations of claim 13. Zhang does not disclose any Bragg reflective layers.
Hwang discloses that the reflective layer 150 comprises a first Bragg reflective layer between the first epitaxial light-emitting structure and the reflective layer (layers 151 and 152 in Hwang figure 10; they can have different refractive indices and act as a Bragg reflector, Hwang paragraph 0094); and a second Bragg reflective layer between the second epitaxial light-emitting structure and the reflective layer (layers 154 [labeled 152 above 153] and 155 in Hwang figure 10; they can have different refractive indices and act as a Bragg reflector, Hwang paragraph 0094). These contribute to the reflective property of the intermediate 150, and therefore have the same benefits described above.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the Bragg reflective layers of Hwang in order to reduce light loss.
Regarding claim 16, Zhang in view of Hwang and Chen teaches all of the limitations of claim 13. Zhang does not give structural details to any electrodes that connect the semiconductor layers, nor does Zhang explicitly disclose a first and second film layer structure.
Hwang teaches a first film layer structure which is a film layer structure between the first semiconductor layer and the third semiconductor layer (128 in Hwang figure 18. This is a structure made of a thin layer, which meets the limitation of a film layer structure), and a second film layer structure which is a film layer structure between the second semiconductor layer and the fourth semiconductor layer (138 in Hwang figure 18. This is a structure made of a thin layer, which meets the limitation of a film layer structure). Hwang also teaches that these electron limiting layers prevent leakage current (See Hwang paragraph 0151).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the film layers of Hwang in order to prevent leakage current.
Hwang also teaches an electrode structure that comprises a first extension portion extending from a sidewall of the third semiconductor layer along a sidewall of a first film layer structure to the first semiconductor layer (146 and 142 in Hwang figure 13, see paragraph 0056. The longest portion that extends vertically along the sidewall of the device is therefore also on the sidewalls of all of the semiconductor layers and the film layers, if they are positioned as they are in figure 18); Hwang teaches that this connects semiconductor layers together and that the integral structure allows it to be easily formed (Hwang paragraph 0111).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use this type of structure to connect the light emitting structures of Zhang in parallel because it is a known technique used to connect semiconductor layers and allows for easy formation of the connection.
Hwang’s connections connect the first and fourth semiconductor layers together and the second and third semiconductor layers together, however, this is because Hwang’s device is arranged in anti-parallel (Hwang paragraph 0062). In connecting the device in parallel, as for Zhang’s device, this connection would naturally go from the top of the third semiconductor layer and extend down to the first semiconductor.
Regarding the second polar electrode, it would be obvious to use this same structure to connect the second and fourth semiconductor layers, since it would accomplish the same result and have the same benefits as discussed above. In order to connect the second and fourth layers using this method, the electrode would naturally go from the top of the fourth semiconductor layer and extend down to the second semiconductor structure. In doing so, the extension portion (long vertical section similar to the 146 to 142 connection in Hwang figure 13) would extend from a sidewall of the fourth semiconductor layer along a sidewall of a second film layer structure (128 in Hwang figure 18) to the second semiconductor layer.
Regarding claim 17, Zhang in view of Hwang and Chen teaches all of the limitations of claim 16. The electrode structure of the combined device further shows that the sidewall of the third semiconductor layer, a sidewall of the first film layer structure, and a sidewall of the first semiconductor layer are connected together to form a first step structure (Hwang figure 13), a step surface of the first step structure is the first semiconductor layer (Hwang figure 13. See cut portion of 122 that connects with 142), and the first extension portion extends from the sidewall of the third semiconductor layer along the sidewall of the first film layer structure to the step surface of the first step structure (The longest portion that extends vertically along the sidewall of the device is therefore on the sidewalls of the third semiconductor layer and the film layer, if the film layer 128 is positioned as it is in figure 18).
Regarding claim 18, Zhang in view of Hwang and Chen teaches all of the limitations of claim 16. The second electrode structure of the combined device further shows that the sidewall of the fourth semiconductor layer, a sidewall of the second film layer structure, and a sidewall of the second semiconductor layer are connected together to form a second step structure (In order to connect the second and fourth electrodes, the structure would look like the 142 – 146 connection in Hwang figure 13, except stopping at a cut portion of the second semiconductor layer [126]), a step surface of the second step structure is the second semiconductor layer (cut portion of 122 would be in 126 to connect to the second semiconductor layer), and the second extension portion extends from the sidewall of the fourth semiconductor layer to the step surface of the second step structure along the sidewall of the second film layer structure (The longest portion extends vertically along the sidewall of the device particularly the sidewalls of the fourth semiconductor layer and the film layer, if the film layer is positioned as it is in figure 18).
Regarding claim 19, Zhang in view of Hwang and Chen teaches all of the limitations of claim 16. The electrode structure of the combined device further shows that the first polar electrode further comprises a first contact portion connected to the first extension portion and in contact with a surface of the third semiconductor layer which faces away from the reflective layer (portion of the electrode on top of the fourth semiconductor layer in Hwang figure 13 that connects to the long vertical portion. For the first electrode which connects the first and third semiconductor layers, this would be on top of the third semiconductor layer); the second polar electrode further comprises a second contact portion connected to the second extension portion and in contact with a surface of the fourth semiconductor layer which faces away from the reflective layer (portion of the electrode on top of the fourth semiconductor layer in Hwang figure 13 that connects to the long vertical portion. For the second electrode which connects the second and fourth semiconductor layers, this would be on top of the fourth semiconductor layer, like in figure 13).
Regarding claim 20, Zhang in view of Hwang and Chen teaches all of the limitations of claim 16. Hwang further teaches a first insulating layer that is located between the first extension portion and the first film layer structure and electrically isolates the first extension portion from the first film layer structure (148 in Hwang figure 13. Hwang paragraph 0110); Hwang teaches that this prevents unnecessary short-circuits.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the insulating layer from Hwang in order to prevent unnecessary short-circuits.
As the two electrodes of the combined have the same essential structure, it would be obvious to add a similar insulating layer between the second electrode and the device stack as well for the same reason of preventing unnecessary short-circuits. Thus, the combined device shows a second insulating layer that is located between the second extension portion and the second film layer structure, and that electrically isolates the second extension portion from the second film layer structure.
Conclusion
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/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
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