Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 7 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “ones” in claims 7 and 15 is a relative term that renders the claim indefinite. The term “ones” does not clearly define what element of the claimed invention is being referred to. Thus, it is unclear what should be included in the prior art in order to read on the claim.
For purposes of examination, the claims are interpreted by the examiner as follows:
Claim 7: “… wherein each of the straight lines is provided with multiple
Claim 15: “… at least some adjacent
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 8-11, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yan et al. (US 20240272753 A1) hereinafter referred to as "Yan", in view of Hyun et al. (US20200357877 A1) hereinafter referred to as "Hyun".
Regarding claim 1, Yan teaches a display panel, having a display area (Fig. 2, element AA; ¶: [0068]) and a peripheral area (Fig. 2, element WA; ¶: [0068]) outside the display area, comprising: a driving backplane (Fig. 4, element BP; ¶: [0073]), comprising a substrate (Fig. 4, element SU; ¶: [0075]) and a transistor layer (Fig. 4, ¶: [0078]), a first conductive layer (Fig. 4, element SD1; ¶: [0078]), a first planarization layer (Fig. 4, element PLN1; ¶: [0078]) and a second conductive layer (Fig. 4, element SD2; ¶: [0078]) sequentially provided in a direction away from the substrate; wherein the transistor layer comprises a plurality of transistors (Fig. 4, ¶: [0078]); the first conductive layer comprising a first conductive line (Fig. 13, element CL; ¶: [0133]) at least partially located in the display area; the second conductive layer comprising a power line (¶: [0078]) and a second conductive line (Fig. 14, element BL; ¶: [0133]) spaced from each other, and both the power line and the second conductive line being at least partially located in the display area; the second conductive line being connected to the first conductive line through a plurality of contact holes (¶: [0124, 0128]) penetrating the first planarization layer, the contact holes being arranged in a row direction and a column direction, a spacing between any two adjacent contact holes in the row direction being a first hole spacing (Fig. 11, element HOL1; ¶: [0138]), some contact holes having the same first hole spacing in at least two rows of contact holes (Fig. 11, element HOL1; ¶: [0138]), a light-emitting device (Fig. 4, element OL; ¶: [0073]) provided on a side of the second conductive layer away from the substrate and located in the display area; wherein the light-emitting device comprises a first electrode (Fig. 4, element ANO; ¶: [0077]), a light-emitting layer (Fig. 4, element EL; ¶: [0077]) and a second electrode (Fig. 4, element CAT; ¶: [0077]) stacked in sequence in the direction away from the substrate, and the second electrode is connected to the second conductive line (Fig. 4, element CAT; ¶: [0083]).
Yan however does not teach the power line being configured to transmit a first power signal, and the first conductive line and the second conductive line are configured to transmit a second power signal, a spacing between any two adjacent contact holes in the column direction being a second hole spacing, some contact holes having the same second hole spacing in at least two columns of contact holes, and the first electrode being connected to at least one of the transistors through the second conductive layer.
Hyun teaches the power line being configured to transmit a first power signal (¶: [0055, 0060]), and the first conductive line and the second conductive line are configured to transmit a second power signal (¶: [0060]), a spacing between any two adjacent contact holes in the column direction being a second hole spacing (Fig. 4, element CNT1, CNT2; ¶: [0097]), some contact holes having the same second hole spacing in at least two columns of contact holes (Fig. 4, element CNT1, CNT2; ¶: [0097]), and the first electrode being connected to at least one of the transistors through the second conductive layer (Fig. 8, element 151, TFT ST, TFT DT; ¶: [0118]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange contact holes in a column fashion so as to not interfere with light-emitting regions (¶: [0097]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect the first electrode to one of the transistors so that the light-emitting device has a connection to the pixel circuit (¶: [0118]).
Regarding claim 2, Yan in view of Hyun teach the display panel according to claim 1, wherein at least some of the contact holes are divided into a plurality of hole groups (Fig. 11, element HOL1, HOL2; ¶: [0138]), and the respective hole groups are arranged in a plurality of rows along the column direction (Fig. 11, element HOL1, HOL2; ¶: [0138]).
Yan however does not teach one of the hole groups comprising some of the contact holes, and the contact holes in the one of the hole groups being arranged along a zigzag track.
Hyun teaches one of the hole groups comprising some of the contact holes, and the contact holes in the one of the hole groups being arranged along a zigzag track (Fig. 4, element CNT1, CNT2; ¶: [0131]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange contact holes in a column fashion so as to not interfere with light-emitting regions (¶: [0097]).
Regarding claim 8, Yan in view of Hyun teach the display panel according to claim 1. Yan further teaches the first hole spacings of contact holes in the same row being the same (Fig. 11, element HOL1, HOL2; ¶: [0138]).
Regarding claim 9, Yan in view of Hyun teach the display panel according to claim 1. Yan however does not teach the second hole spacings of contact holes in a same column being the same.
Hyun teaches the second hole spacings of contact holes in a same column being the same (Fig. 4, element CNT1, CNT2; ¶: [0131]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange contact holes in such a fashion so as to not interfere with light-emitting regions (¶: [0097]).
Regarding claim 10, Yan in view of Hyun teach the display panel according to claim 1. Yan further teaches a touch layer (Fig. 3, element TL; ¶: [0063]), provided on a side of the light-emitting device away from the substrate; wherein the touch layer comprises a plurality of touch electrodes (Fig. 3, element Tx, Rx; ¶: [0094]), and the touch electrodes are in a grid structure formed by a plurality of grid lines (Fig. 5, element Tx, Rx; ¶: [0094]); wherein at least some of the contact holes overlap with the grid lines (¶: [0100]).
Regarding claim 11, Yan in view of Hyun teach the display panel according to claim 10. Yan further teaches the touch electrodes comprising a plurality of first touch electrodes (Fig. 3, element Tx; ¶: [0094]) and a plurality of second touch electrodes (Fig. 3, element Rx; ¶: [0094]), the respective first touch electrodes being spaced apart along the row direction (¶: [0094]), and one of the first touch electrodes comprises a plurality of first electrode blocks (Fig. 3, element Txc; ¶: [0095]) spaced apart along the column direction and a connecting bridge (Fig. 3, element BR; ¶: [0095]) connecting any adjacent two of the first electrode blocks; the respective second touch electrodes are spaced apart along the column direction (¶: [0094]), and one of the second touch electrodes comprises a plurality of second electrode blocks (Fig. 3, element Rxc; ¶: [0095]) connected in series along the row direction; one of the connecting bridges is arranged crosswise with one of the second touch electrodes (Fig. 3, element BR; ¶: [0095]); the first electrode blocks and the second electrode are located in a same electrode layer (¶: [0099]); and the connecting bridges are located on one side of the electrode layer (¶: [0097]); the touch layer further comprises a touch insulating layer (Fig. 3, element IN; ¶: [0096-0098]) located between the connecting bridges and the electrode layer, and the connecting bridges are connected to the first electrode blocks through a via hole penetrating the touch insulating layer (¶: [0099-0100]).
Regarding claim 17, Yan teaches a display device, comprising a display panel, having a display area (Fig. 2, element AA; ¶: [0068]) and a peripheral area (Fig. 2, element WA; ¶: [0068]) outside the display area, comprising: a driving backplane (Fig. 4, element BP; ¶: [0073]), comprising a substrate (Fig. 4, element SU; ¶: [0075]) and a transistor layer (Fig. 4, ¶: [0078]), a first conductive layer (Fig. 4, element SD1; ¶: [0078]), a first planarization layer (Fig. 4, element PLN1; ¶: [0078]) and a second conductive layer (Fig. 4, element SD2; ¶: [0078]) sequentially provided in a direction away from the substrate; wherein the transistor layer comprises a plurality of transistors (Fig. 4, ¶: [0078]); the first conductive layer comprising a first conductive line (Fig. 13, element CL; ¶: [0133]) at least partially located in the display area; the second conductive layer comprising a power line (¶: [0078]) and a second conductive line (Fig. 14, element BL; ¶: [0133]) spaced from each other, and both the power line and the second conductive line being at least partially located in the display area; the second conductive line being connected to the first conductive line through a plurality of contact holes (¶: [0124, 0128]) penetrating the first planarization layer, the contact holes being arranged in a row direction and a column direction, a spacing between any two adjacent contact holes in the row direction being a first hole spacing (Fig. 11, element HOL1; ¶: [0138]), some contact holes having the same first hole spacing in at least two rows of contact holes (Fig. 11, element HOL1; ¶: [0138]), a light-emitting device (Fig. 4, element OL; ¶: [0073]) provided on a side of the second conductive layer away from the substrate and located in the display area; wherein the light-emitting device comprises a first electrode (Fig. 4, element ANO; ¶: [0077]), a light-emitting layer (Fig. 4, element EL; ¶: [0077]) and a second electrode (Fig. 4, element CAT; ¶: [0077]) stacked in sequence in the direction away from the substrate, and the second electrode is connected to the second conductive line (Fig. 4, element CAT; ¶: [0083]).
Yan however does not teach the power line being configured to transmit a first power signal, and the first conductive line and the second conductive line are configured to transmit a second power signal, a spacing between any two adjacent contact holes in the column direction being a second hole spacing, some contact holes having the same second hole spacing in at least two columns of contact holes, and the first electrode being connected to at least one of the transistors through the second conductive layer.
Hyun teaches the power line being configured to transmit a first power signal (¶: [0055, 0060]), and the first conductive line and the second conductive line are configured to transmit a second power signal (¶: [0060]), a spacing between any two adjacent contact holes in the column direction being a second hole spacing (Fig. 4, element CNT1, CNT2; ¶: [0097]), some contact holes having the same second hole spacing in at least two columns of contact holes (Fig. 4, element CNT1, CNT2; ¶: [0097]), and the first electrode being connected to at least one of the transistors through the second conductive layer (Fig. 8, element 151, TFT ST, TFT DT; ¶: [0118]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange contact holes in a column fashion so as to not interfere with light-emitting regions (¶: [0097]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect the first electrode to one of the transistors so that the light-emitting device has a connection to the pixel circuit (¶: [0118]).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Yan in view of Hyun and further in view of Jeong et al. (US20200381486 A1) hereinafter referred to as "Jeong".
Regarding claim 6, Yan in view of Hyun teaches the display panel according to claim 1. Neither reference teaches at least some of the contact holes being arranged along a track formed by a plurality of radially distributed straight lines intersecting at a same intersection.
Jeong teaches at least some of the contact holes (Fig. 14, element CNT1, CNT2, CNT4, CNT5; ¶: []) being arranged along a track formed by a plurality of radially distributed straight lines (Fig. 14, element 501, 503; ¶: [0137, 0144, 0147]) intersecting at a same intersection.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply this arrangement so as to prevent or minimize damage due to static electricity (¶: [0147]).
Regarding claim 7, Yan in view of Hyun and Jeong teaches the display panel according to claim 6. Neither Yan nor Hyun teaches each of the straight lines being provided with multiple contact holes, and numbers of contact holes on each of the straight lines being the same.
Jeong teaches each of the straight lines being provided with multiple contact holes, and numbers of contact holes on each of the straight lines being the same (Fig. 14, element 501, 503, CNT1, CNT2, CNT4, CNT5; ¶: [0137, 0144, 0147]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply this arrangement so as to prevent or minimize damage due to static electricity (¶: [0147]).
Allowable Subject Matter
Claims 3-5,12-16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 4-5 are objected to due to their dependence on claim 3. Claims 13-14 are objected to due to their dependance on claim 12.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Regarding claims 3 and 12, Yan is cited as teaching some elements of the claimed invention such as the driving backplane, the arrangement of contact holes as well as their orthographic projection. However, the prior art, alone or in combination cannot be construed as teaching or suggesting all of the elements involved in the claimed invention as claimed by the applicant.
Regarding claim 3, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the contact holes in the one of the hole groups are arranged along a V-shaped track.”, as recited in Claim 3, with the remaining features.
Regarding claim 12, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein an orthographic projection of a contact hole on the substrate is located within an orthographic projection, on the substrate, of a grid line overlapping with the contact hole.”, as recited in Claim 12, with the remaining features.
Regarding claim 15, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " and a width of the connecting intersection is greater than a width of the connecting line connected to the connecting intersection;”, as recited in Claim 15, with the remaining features.
Regarding claim 16, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " the data line, the power line and the second conductive line all extend along the column direction and are spaced apart along the row direction; …the data line and the power line connected to the pixel circuits in a same column form a line group,”, as recited in Claim 16, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/I.H./ Examiner, Art Unit 2899
/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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