DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 and 8 objected to because of the following informalities:
As per Claim 1:
Line 3, the phrase “the clock control signal is located” should be --the clock control signal being located-- for proper grammar.
Line 5, the phrase “according to and a second clock gating circuit” should be --according to a second clock gating circuit-- for proper grammar.
Line 12, the phrase “an valid state” should be --a valid state-- for proper grammar.
As per Claim 8:
Line 4, the phrase “third clock gating circuit” should be --a third clock gating circuit -- for proper grammar.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-8, and 16-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the second clock signal" in line 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites the limitation "the first clock gating circuits" in line 9. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites the limitation "the second clock gating circuit" in each of lines 9, 16, and 17. There is insufficient antecedent basis for these limitations in the claim, because the claim recites two instances of “a second clock gating circuit” in each of line 4 and line 5, and therefore it is unclear as to which of these is being referred to by the claim limitations.
Claim 1 recites the limitation "the starting edge" in line 13. There is insufficient antecedent basis for this limitation in the claim.
Claim 3 recites the limitation "the second clock gating circuit" in line 2. There is insufficient antecedent basis for this limitation in the claim, because Claim 1 on which Claim 3 depends recites two instances of “a second clock gating circuit” in each of line 4 and line 5, and therefore it is unclear as to which of these is being referred to by the claim limitation.
Claim 4 recites the limitation "the second clock gating circuit" in line 2. There is insufficient antecedent basis for this limitation in the claim, because Claim 1 on which Claim 4 depends recites two instances of “a second clock gating circuit” in each of line 4 and line 5, and therefore it is unclear as to which of these is being referred to by the claim limitation.
Claim 5 recites the limitation "the second clock gating circuit" in line 2. There is insufficient antecedent basis for this limitation in the claim, because Claim 1 on which Claim 5 depends recites two instances of “a second clock gating circuit” in each of line 4 and line 5, and therefore it is unclear as to which of these is being referred to by the claim limitation.
Claim 7 recites the limitation "the second clock gating circuit" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim, because Claim 1 on which Claim 7 depends recites two instances of “a second clock gating circuit” in each of line 4 and line 5, and therefore it is unclear as to which of these is being referred to by the claim limitation.
Claim 8 recites the limitation "the clock cycle during which the clock control signal is flipped" in line 7. There is insufficient antecedent basis for this limitation in the claim.
Claim 16 recites the limitation "the predetermined level" in line 2. There is insufficient antecedent basis for this limitation in the claim, as both claim 1 and claim 8 on which claim 16 depends recites an instance of “a predetermined level” (See Claim 1, Line 11 and Claim 8, Line 6), and therefore it is unclear as to which of these is being referred to by the claim limitation.
Claim 17 recites the limitation "the flip-flop unit" in line 2. There is insufficient antecedent basis for this limitation in the claim, as claim 1 on which claim 17 depends recites two instances of “a flip-flop unit” in each of lines 1 and lines 7-8, and therefore it is unclear as to which of these is being referred to by the claim limitation.
Claim 20 recites the limitation "the flip-flop unit" in line 2. There is insufficient antecedent basis for this limitation in the claim, as claim 1 on which claim 20 depends recites two instances of “a flip-flop unit” in each of lines 1 and lines 7-8, and therefore it is unclear as to which of these is being referred to by the claim limitation.
Claim 24 recites the limitation "the second clock gating circuit" in line 2. There is insufficient antecedent basis for these limitations in the claim, because Claim 1 on which Claim 24 depends recites two instances of “a second clock gating circuit” in each of line 4 and line 5, and therefore it is unclear as to which of these is being referred to by the claim limitations.
Claims 6, 18-19, and 21-23 are rejected based on their dependency to Claims 1, 17, and 20, respectively, for the reasons stated above.
Allowable Subject Matter
Claims 1, 3-8, and 16-24 would be allowable if the claim objections and 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph rejections set forth above are overcome.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 1, Jain et al., hereinafter Jain, US Patent No. 9,317,639 teaches a design method for a flip-flop unit, comprising:
coupling at least one edge-triggered flip-flop and the selected clock gating circuit to be a flip-flop unit, the edge-triggered flip-flop transmitting data at an edge of the second clock signal (Jain Col. 9, Lines 12-17, wherein OR type or AND type clock gating circuits are connected to positive-edge or negative-edge triggered flip flops),
wherein the first clock gating circuits and the second clock gating circuit maintain the second clock signal at a predetermined level at least in a clock cycle during which the clock control signal flips from an valid state to an invalid state (Jain Col. 1, Lines 64-67, Col. 2, Lines 1-8, and Col. 4, Lines 9-49, wherein latched clock gating holds the logic state of the output signal regardless of transitions during a clock cycle),
in a case that the starting edge of the first-level phase is a rising edge, the first clock gate circuit is selected, wherein the first clock gating circuit performs a combinational logic operation comprising at least a logical OR operation on the clock control signal and the first clock signal (Jain Fig. 3A and Col. 9, Lines 5-17, wherein OR type clock gating circuits are connected to positive-edge triggered flip flops, the OR being performed on a latched enable signal and the clock),
in a case that the starting edge of the first-level phase is a falling edge, the second clock gate circuit is selected, wherein the second clock gating circuit performs a combinational logic operation comprising at least a logical AND operation on the clock control signal and the first clock signal (Jain Fig. 3B and Col. 7, Lines 9-20 and Col. 9, Lines 5-17, wherein AND type clock gating circuits are connected to negative-edge triggered flip flops, the AND being performed on a latched enable signal and the clock).
The prior art of record does not teach or suggest the following claim limitations:
analyzing signal delay of a clock control signal relative to a first clock signal in a digital circuit;
upon a delay range of the clock control signal is located in a first-level phase of the first clock signal, selecting one of a first clock gating circuit and a second clock gating circuit according to and a second clock gating circuit.
Claims 3-8 and 16-24 would be allowable based on their dependency to Claim 1 for the reasons stated above.
Conclusion
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/ERIC D LEE/Primary Examiner, Art Unit 2851
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