DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to Application filed on 07/23/2024
Application is a 371 of PCT/JP2022/047557 12/23/2022
Application claims a FP date of 01/31/2022
Claim 1 is independent
Claims 1-16 are pending
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in the instant Application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/23/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3, 5-6 and 13 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims recite “outputs a predetermined number of clock pulses” contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The instant Specification just recites the claim multiple times, however Applicant fails to provide drawings or description which is described in such as way so as to reasonably convey to one skilled in the art to make or use the invention.
Claim 4 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims recite “the first number of clock pulses and the second number of clock pulses are generated so as to make the high-level signal or the low-level signal of each bit set on a basis of count of the second number of clock pulses inverse to the high-level signal or the low-level signal of each bit set on a basis of count of the first number of clock pulses” contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The instant Specification just recites the claim multiple times, however Applicant fails to provide drawings or description which is described in such as way so as to reasonably convey to one skilled in the art to make or use the invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Regarding claim 4, the claim recites “the first number of clock pulses and the second number of clock pulses are generated so as to make the high-level signal or the low-level signal of each bit set on a basis of count of the second number of clock pulses inverse to the high-level signal or the low-level signal of each bit set on a basis of count of the first number of clock pulses”. The language of the claim is unclear as it is not clear the conditions recited to set each bit. This one of ordinary skill in the art would not be able to reasonably apprised of the scope of the invention and understand what exactly is being claimed. Therefor the claim is "indefinite". See MPEP 2173.05(g) for more information.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 and 12-14 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Ryoki et al. (U.S. Patent Publication Number 2021/0123802 A1).
Regarding Claim 1, Ryoki discloses a light-receiving element (Fig 1 discloses an image capturing apparatus 100) comprising:
a plurality of pixels (In fig 1 and in ¶0024, Ryoki discloses that the image capturing apparatus 100 includes a plurality of pixel circuits 110); and
a control circuit (Fig 1- TG 102 is a control circuit for generating a signal for controlling each of the units of image capturing apparatus 100), wherein
each of the pixels (Fig 1- pixels circuits 110) includes:
a sensing circuit capable of detecting an incident photon (Fig 10 AVD 111 which is an avalanche diode); and
a counter circuit (Fig 1- counter 114) that counts pulses output from the sensing circuit or clock pulses output from the control circuit (In ¶0032, Ryoki discloses that the counter 114 counts the number of occurrences of pulses of the pulse signal output from the inverter 113), and
the counter circuit counts the clock pulses (In ¶0041, Ryoki discloses that a clock pulse is input to the Vbias generation circuit 118 from the clock pulse generation unit) output from the control circuit in an inspection mode (Examiner would like to state that “inspection mode” has not been defined in the claim. However, Ryoki discloses the “non-Geiger mode” or the “testing mode” which has been interpreted as “an inspection mode”).
Regarding Claim 2, Ryoki discloses wherein the counter circuit counts the pulses output (In ¶0008 and throughout, Ryoki discloses that the counter is configured to count a number of occurrences of the first pulse signal) from the sensing circuit in an imaging mode (The “regular mode” or “Geiger mode” disclosed by Ryoki is interpreted as “an imaging mode”).
Regarding Claim 3, Ryoki discloses wherein the control circuit outputs a predetermined number of clock pulses in the inspection mode (In ¶0040-¶0041, Ryoki discloses that in a “non-Geiger mode” also “testing mode” which has been interpreted as “the inspection mode” a clock pulse is input to the Vbias generation circuit from the clock pulse generation unit. In ¶0080, he also discloses that the frequency of the second pulse may conform to a predetermined divided frequency of the clock pulse).
Regarding Claim 4, Ryoki discloses wherein the counter circuit is a multi-bit counter (Ryoki in ¶0032, discloses that the counter has a bit width which is 16 bits, It is clear that Ryoki discloses a multi-but counter) in which a high-level signal or a low-level signal is set for each bit on a basis of a number of pulses (In ¶0032, Ryoki also discloses that the counter 114 having a bit width of 16 is 65535 in decimal notation, which is clear that the high level or low level is based on the count of the pulse signals),
the control circuit resets the counter circuit after outputting a first number of clock pulses (In ¶0032 he also discloses that the a reset control signal RES is input to the counter), and outputs a second number of clock pulses different from the first number, and
the first number of clock pulses and the second number of clock pulses are generated so as to make the high-level signal or the low-level signal of each bit set on a basis of count of the second number of clock pulses inverse to the high-level signal or the low-level signal of each bit set on a basis of count of the first number of clock pulses. (Ryoki discloses this in Fig 7 and in ¶0103 - ¶0117).
Regarding Claim 5, Ryoki discloses wherein the counter circuit is a multi-bit counter (Ryoki in ¶0032, discloses that the counter has a bit width which is 16 bits, It is clear that Ryoki discloses a multi-but counter) capable of initializing each bit with an initial value (In ¶0032 he also discloses that the a reset control signal RES is input to the counter), and
the control circuit sets the initial value for each bit and outputs a predetermined number of clock pulses (In ¶0025, Ryoki discloses that the TG 102 supplies a reset control signal RES to each of the pixel circuits 110; also see ¶0032 and ¶0047-¶0048 and in ¶0058 he discloses that when the reset control signal RES is at a low level the counter 114 is counter is brought to a state where counting can be started.).
Regarding Claim 6, Ryoki discloses wherein the counter circuit is a multi-bit counter (Ryoki in ¶0032, discloses that the counter has a bit width which is 16 bits, It is clear that Ryoki discloses a multi-but counter) capable of initializing each bit with an initial value (In ¶0032 he also discloses that the a reset control signal RES is input to the counter), and
the control circuit sets the initial value (The RES signal discloses sets the initial value) for each bit and outputs a clock pulse to a predetermined bit (In ¶0041, Ryoki discloses that the Vbias generation circuit outputs pulse signals which is a reference circuit without depending on incident light).
Regarding Claim 7, Ryoki discloses wherein each of the pixels further includes:
an avalanche photodiode (Ryoki’s invention incudes an avalanche diode);
a resistor (Fig 1- resistor 112) connected in series (Fig 1 discloses that the resistor 112 is connected to the avalanche diode 111) to the avalanche photodiode (Fig 1- Avalanche photodiode 111) between a power supply terminal (Fig 1- Vbias) and a ground terminal (Fig 1 discloses the ground terminal); and
a waveform shaping circuit (Fig 1- Invertor 113 is a waveform shaping circuit; See ¶0026) that shapes an output signal of the avalanche photodiode into the pulses (Since the inverter 113 is connected to the cathode of the AVD 111 the inverter 113 serves as a waveform shaping circuit that converts the potential of the cathode of the AVD 111 to a pulse signal as disclosed in ¶0031).
Regarding Claim 8, Ryoki discloses further comprising a memory (Fig 1- column memory unit 103) that stores coordinates of an unusual pixel whose operation is unusual among the plurality of pixels (In ¶0054 Ryoki discloses about “defective” pixels – whose signals does not conform to the expectation value are deemed as “defective”. Further in the same paragraph, Ryoki discloses that the “address” of the defective pixel is specified. Therefore it is reasonable to say to Ryoki discloses “storing coordinates of an unusual pixel”).
Regarding Claim 12, Ryoki discloses further comprising a reading circuit that reads count from the counter circuit of each of the plurality of pixels in accordance with coordinates of the pixel (¶0033, ¶0073; Ryoki also discloses the “reading control line” arranged in each row of the pixel circuit 100).
Regarding Claim 13, Ryoki discloses a determination circuit that sequentially compares the count read by the reading circuit from the counter circuit of each of the pixels with a predetermined number and determines whether or not the counter circuit of each of the pixels is faulty in the inspection mode (Ryoki discloses this in ¶0008 where he discloses that the testing whether the photoelectric conversion apparatus is “normal” by comparing a digital signal acquired by the counter counting the second pulse signal with an expectation value. Also see ¶0043 and ¶0054).
Regarding Claim 14, Ryoki discloses wherein the determination circuit (In ¶0130, Ryoki discloses that the signal processing unit 1007 can be operated as the comparison circuit) causes the memory to store coordinates of a pixel including the counter circuit determined to be faulty (In ¶0054, Ryoki discloses that address of the defective pixel is specified and in ¶0043, Ryoki discloses that the “expectation value is a value corresponding to the number of pulses of the second pulse signal counted throughout a period in which the counter 114 counts the number of occurrence of the second pulse signal.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ryoki et al. (U.S. Patent Publication Number 2021/0123802 A1).
Regarding Claim 15, Ryoki discloses all the features of Claim 14 except wherein the determination circuit is detachable. It would have been obvious to one having ordinary skill in the art at the time the invention was made to the determination circuit is detachable, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. Nerwin v. Erlichman, 168 USPQ 177, 179.
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over Ryoki et al. (U.S. Patent Publication Number 2021/0123802 A1) in view of Hikosaka (U. S. Patent Publication Number 2023/0224609 A1 which has a FP date of Jan 13, 2022).
Regarding Claim 16, Ryoki fails to clearly disclose further comprising an optical system that supplies imaging light to the light-receiving element.
Instead in a similar endeavor, Hikosaka discloses further comprising an optical system that supplies imaging light to the light-receiving element (Fig 17 – light source device 320 that provides light towards an object 330; In Fig 18 Hikosaka teaches about light source device 434 that supplies light to the imaging device).
Ryoki and Hikosaka are combinable because both are related to imaging device devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the light source device as taught by Hikosaka in the imaging module disclosed by Ryoki.
The suggestion/motivation for doing so would have been to “provide light to the imaging device” as disclosed by Hikosaka in ¶0144.
Therefore, it would have been obvious to combine Ryoki and Hikosaka to obtain the invention as specified in claim 16.
Allowable Subject Matter
Claims 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reference Cited
The following prior art made of record but not relied upon is considered pertinent to applicant's disclosure.
Kumaki et al. (U.S. Patent Publication Number 2019/0289213 A1) discloses an image sensor that obtains an image in which shake is corrected, while at the same time suppresses an increase in the circuit size, is disclosed. The image sensor has a plurality of pixels. Each of the plurality of pixels includes a light-sensitive element that detects the incidence of single photons; and a counter that counts a pulse contained in a signal. The image sensor further comprises a control unit that, on the basis of detected shake, switches a signal of the light-sensitive element supplied to the counter in a pixel, or replaces a count value of the counter of the pixel with a count value of the counter in another pixel.
Conclusion
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/PADMA HALIYUR/Primary Examiner, Art Unit 2639 October 28, 2025