Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The Office has cited particular columns, line numbers, paragraph numbers, references, or figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-15, 17, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kiyomizu (US 2010/0033223 A1, hereinafter referred to as Kiyomizu).
Regarding claim 1, Kiyomizu discloses a flip-flop unit (Figs. 1, 6, 7, 10, 14), comprising:
an edge-triggered flip-flop (12, 126) having a data input terminal (D), a clock input terminal (CK), and a first data output terminal (Q),
and a clock gating circuit having a first input terminal, a second input terminal, a clock input terminal and an output terminal ("clock signal output section 14 ... XNOR circuit 16 and OR circuit 18" - para. [0041]; FIG. 1)
wherein the first input terminal of the clock gating circuit receives input data (IN) of the edge-triggered flip-flop ("data signal IN... to one input terminal of the XNOR circuit 16" - para. [0042])
the second input terminal of the clock gating circuit receives output data (OUT) of the edge-triggered flip-flop ("output data signal... from the data output terminal Q ... to the other input terminal of the XNOR circuit 16" - para [0042])
the clock input terminal of the clock gating circuit receives a first clock signal ("clock signal CLK ... to the other input terminal of the OR circuit 18" - para. [0043])
and the output terminal (B) of the clock gating circuit is coupled to the clock input terminal of the edge-triggered flip-flop to provide a second clock signal ("clock signal B ... to the clock input terminal CK of the D-flip-flop 12" - para. [0043])
the clock gating circuit enables or disables the first clock signal to generate the second clock signal according to a data comparison result of the input data and the output data ("only when the data signal IN changes" via XNOR - para. [0044])
so that the second clock signal provides a triggering edge of the edge-triggered flip-flop ("in synchronism with the rise of the clock signal" - para. [0044])
the clock gating circuit copies the first clock signal as the second clock signal in a clock cycle during which the input data is flipped ("outputs a clock signal CLK in synchronism with the rise... only when the data signal IN changes" - para. [0044])
and maintains the second clock signal at a predetermined level in clock cycles during which the input data remains unchanged (no clock output when data stable - para. [0044]; FIG. 2),
wherein the edge-triggered flip-flop is a D-type flip-flop (12, 126).
Regarding Claim 2, Kiyomizu discloses the flip-flop unit according to claim 1, wherein each clock cycle (CLK, Fig. 2) of the first clock signal has a first-level phase (CLK up) and a second-level phase (CLK down) successively, and the input data (IN) is flipped in the first-level phase (IN up) of the first clock signal (see Fig. 2).
Regarding Claim 3, Kiyomizu discloses the flip-flop unit according to claim 2, wherein the predetermined level is a level of the first-level phase (up), and the second clock signal (B) provides a triggering edge in the next clock cycle following the clock cycle during which the input data is flipped ("only when the data signal IN changes" in subsequent cycle - para. [0049]; FIG. 2).
Regarding Claim 4, Kiyomizu discloses the flip-flop unit according to claim 2, wherein
a starting edge of the first-level phase is a rising edge ("in synchronism with the rise of the clock signal" - para. [0044]).
Regarding Claim 5, Kiyomizu discloses the flip-flop unit according to claim 4, wherein the clock gating circuit (14, Fig. 1, 6) comprises: an XOR gate (16, “a negation signal A which is a negation of the exclusive OR of the data signal IN and the output data signal”, para [0042]) having a first input terminal, a second input terminal and an output terminal, the first input terminal and the second input terminal respectively receiving the input data and the output data of the edge-triggered flip-flop, and the output terminal providing a first clock control signal; an OR gate (18) having a first input terminal, a second input terminal, and an output terminal, the first input terminal receiving the first clock signal, and a NOT gate (inversion circuit at the output of XOR 16) having an input terminal and an output terminal, the NOT gate being coupled between the output terminal of the XOR gate and the second input terminal of the OR gate, wherein the first clock control signal is inverted by the NOT gate and the inverted first clock control signal is provided to the second input terminal of the OR gate, and the second clock signal is provided by the output terminal of the OR gate (paras. [0042]-[0043]).
Regarding claim 6, Kiyomizu discloses the flip-flop unit according to claim 5, wherein the OR gate (18) further comprises a third input terminal (input of 22 connected to SCAN_EN) receiving an inverted signal (see inversion circuit at the input of 22) of a second clock control signal (SCAN_EN).
Regarding claim 7, Kiyomizu discloses the flip-flop unit according to claim 6, wherein the clock gating circuit enables (by SCAN_EN connected to 24) a data comparison function (normal operation) when the second clock control signal (SCAN_EN) is valid (SCAN_EN: “L”), and the clock gating circuit disables data comparison function (scan test) when the second clock control signal is invalid (SCAN_EN: “H”; para [0065])
Regarding Claim 8, Kiyomizu discloses the flip-flop unit according to claim 2, wherein a starting edge of the first-level phase is a falling edge (see Fig. 8).
Regarding Claim 9, Kiyomizu discloses the flip-flop unit according to claim 8, wherein the clock gating circuit (34, Fig. 7, 10) comprises: an XOR gate (36, Fig. 7) having a first input terminal, a second input terminal, and an output terminal, the first input terminal and the second input terminal receiving the input data and the output data of the edge- triggered flip-flop, respectively, and the output terminal providing a first clock control signal; and an AND gate (38) having a first input terminal, a second input terminal, and an output terminal, the first input terminal receiving the first clock signal, the second input terminal receiving the first clock control signal, and the output terminal providing the second clock signal (see Fig. 7) .
Regarding Claim 10, Kiyomizu discloses the flip-flop unit according to claim 8, wherein the AND gate (38, Fig. 10) further comprises a third input terminal (input of 42 connected to SCAN_EN), and the third input terminal receives a second clock control signal (SCAN_EN, Fig. 10).
Regarding Claim 11, Kiyomizu discloses the flip-flop unit according to claim 10, wherein the clock gating circuit (34, Fig. 7, 10) enables (by SCAN_EN connected to 44) a data comparison function (normal operation) when the second clock control signal is valid (SCAN_EN: “L”), and the clock gating circuit disables data comparison function (scan test) when the second clock control signal is invalid (SCAN_EN: “H”; para [0086]).
Regarding Claim 12, Kiyomizu discloses the flip-flop unit according to claim 5, wherein the input data (D, Fig. 1) of the edge- triggered flip-flop (12) is an inverted signal (QN) of the output data (Q, OUT) of the edge-triggered flip-flop, and wherein the data input terminal (D) of the edge-triggered flip-flop receives the inverted signal (QN) of the output data (OUT) as input data (D).
Regarding Claim 13, Kiyomizu discloses the flip-flop unit according to claim 12, wherein the edge-triggered flip-flop (12, Fig. 1) further comprises a second data output terminal (QN), and provides the output data (OUT) of the edge-triggered flip-flop at the first data output terminal (Q), and provides the inverted signal (QN) of the output data (OUT) at the second data output terminal (QN), wherein the data input terminal (D) and the second data output terminal (QN) of the edge-triggered flip-flop are coupled to each other to receive the inverted signal of the output data (QN; see Fig. 1).
Regarding Claim 14, Kiyomizu discloses the flip-flop unit according to claim 6, wherein each of the first clock control signal (OUT) and the second clock control signal (SCAN_EN) indicates a valid state (valid for scan test) with a high level (“H”) and an invalid state (scan test invalid) with a low level (“L”; para [0065]).
Regarding Claim 15, Kiyomizu discloses the flip-flop unit according to claim 8, wherein the edge-triggered flip-flop receives the input data at the data input terminal and transmits the input data to the first data output terminal at the triggering edge ("the data signal input to the data input terminal D ... the output data signal OUT output from the output terminal Q of the D-flip-flop 32 becomes H" - para. [0076]).
Regarding Claim 17, Kiyomizu discloses the flip-flop unit according to claim 5, wherein the input data (D, Fig. 7) of the edge- triggered flip-flop (32) is an inverted signal (QN) of the output data (Q, OUT) of the edge-triggered flip-flop, and wherein the data input terminal (D) of the edge-triggered flip-flop receives the inverted signal (QN) of the output data (OUT) as input data (D).
Regarding Claim 18, Kiyomizu discloses the flip-flop unit according to claim 10, wherein each of the first clock control signal (OUT) and the second clock control signal (SCAN_EN) indicates a valid state (valid for scan test) with a high level (SCAN_EN: “H”) and an invalid state (scan test invalid) with a low level (SCAN_EN: “L”; para [0065]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kiyomizu.
Regarding claim 16, Kiyomizu discloses all the features and limitations as discussed above but does not disclose wherein the flip-flop unit is a library cell in a standard cell library of an EDA tool of digital circuits.
However, it is well-known in the art that a flip-flop is a fundamental building block of digital circuits and a type of cell included in a standard-cell library used by EDA (Electronic Design Automation) tools. These libraries contain pre-designed and characterized logic and sequential components that EDA tools use to implement a digital circuit design during synthesis, placement, and routing.
Therefore, it would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate these well-known features into the device of Kiyomizu in order to utilize the EDA tools to implement a digital circuit design during synthesis, placement, and routing.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL D CHANG whose telephone number is (571)272-1801. The examiner can normally be reached M-F 8-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL D CHANG/ Primary Examiner, Art Unit 2845
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