Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 24-29 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim limitations in claim 24 recites “storing a wake-up policy in an always-on domain of the computer system, the wake-up policy defining processor selection criteria for simultaneous wake-up events;” – processor selection for simultaneous wake-up events. While the claim selection process is performed for single wake up event as the claim recites “detecting a wake-up event while the computer system is in a deep low power state where the at least two processors are not supplied with power; determining, based on the stored wake-up policy and the detected wake-up event, which processor of the at least two processors to wake up first ”- criteria is to select a processor based on the simultaneous wakeup events are received while the claim limitation is directed toward single event received and waking up based on the detected single event which is deviates away from the condition. The claim limitation indefinite as the claim limitations do not provide clarity on disguisable claim limitations. Applicant may change claim limitation ‘…detecting simultaneous wakeup events….’ and ‘...determining, based on the stored wake-up policy and the detected wake-up events…’. Or Applicant is requested to make appropriate change.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10, 11, 14-16, 22, 23 is/are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Hendrich [10664039].
As to claim 10,
Hendrich [10664039] teaches A computer system comprising:
at least two processors [col. 11: line 29-35: “Embodiments may be implemented in many different system types. Referring now to FIG. 11, shown is a block diagram of a system in accordance with an embodiment of the present invention. As shown in FIG. 11, multiprocessor system 600 is a point-to-point interconnect system, and includes a first processor 670 and a second processor 680 coupled via a point-to-point interconnect 650. As shown in FIG. 11, each of processors 670 and 680 may be multicore processors, including first and second processor cores (i.e., processor cores 674a and 674b and processor cores 684a and 684b)”], the computer system having a deep sleep mode in which the processors are not supplied with power [ col 6: line: 3-7: “method 300 may begin by placing both large and small cores in a sleep state (block 310). That is, it is assumed that no active operations are being performed in the cores. As such, they can be placed in a selected low power state to reduce power consumption.” and col. 6: “when both large and small cores are in a low power state” – compute system, is sleep mode when both processors are in low power and no active operation are performed. Sleep mode can be deep sleep mode see col. 11, lines 18: “an active C0 state to a deep low power state”];
a power supply controller configured to detect events of different types that require processing by the at least two processors when the computer system is in deep sleep mode [col.5, line 23-26: “Note that it is also possible that the PCU or another programmable entity may examine incoming wake events to determine which core (large or small) to route them to ” and col. 4,line 64-67: “hardware domain 220 and the mapping of OS C-states to processor C-states can be performed by a power control unit (PCU) of the processor, although the scope of the present invention is not limited in this regard. ”and col.6: “Although the cores may not be active, other agents within a processor or SoC such as one or more accelerators may be performing tasks.” and col. 10, line 66 to col. 11, line 5: “an accelerator can send a hint to the PCU or other management agent with an interrupt to indicate that the requested operation is a relatively simple operation such that it can be handled effectively in the small core. This accelerator-provided hint may be used by the PCU to automatically direct incoming interrupts to the small core for handling” and col. 8, line 27-30]; and
configuration registers configured to assign the processing of each event detected by the power supply controller to the different processors according to the type of event detected [“PCU 450 may include an interrupt history storage 456. Such storage may include a plurality of entries each identifying an interrupt that has occurred during system operation and whether the interrupt was successfully handled by the small core. Then based on this history, when a given interrupt is received, a corresponding entry of this storage can be accessed to determine whether a previous interrupt of the same type was successfully handled by the small core. If so, the PCU can direct the new incoming interrupt to the same small core. Instead if it is determined based on this history that this type of interrupt was not successfully handled by small core (or with unsatisfactorily low performance), the interrupt can instead be sent to a large core. ”];
a wake-up circuit configured to:
disable deep sleep mode after an event is detected by the power supply controller col. 4:18-24: “Embodiments allow the larger, less power-efficient cores to remain in low power sleep states longer than they otherwise would be able to. By steering interrupts and other core waking events to the smaller cores instead of the larger cores,”- disable sleep mode wakes the processor core.], and
activate, when disabling deep sleep mode, a power supply of one of the at least two processor to which the processing of the detected event has been assigned according to the configuration registers, wherein the activation of the power supply powers on the one of the at least two processors, and wherein the powered-on processor is configured to process the detected event [col. 4:18-24: “Embodiments allow the larger, less power-efficient cores to remain in low power sleep states longer than they otherwise would be able to. By steering interrupts and other core waking events to the smaller cores instead of the larger cores, the smaller cores may run longer and wake more often, but this is still more power efficient than waking a large core to perform a trivial task such as data moving. ”- when large core is not waken, power is supplied to smaller core and powered on small core performs function and large core remain in sleep mode and “If instead it is determined at diamond 340 that the small core cannot handle the requested operation, e.g., if the operation is a relatively complex operation that the small core is not configured to handle, control instead passes to block 360. There, a wakeup signal can be sent, e.g., directly from the small core to the large core, to cause the large core to be powered up. Accordingly, control passes to block 370 where the requested operation can thus be performed in the large core. ”].
As to claim 11,
Hendrich teaches The computer system according to claim 10, wherein the configuration registers are further configured to define which of the at least two processors to wake up first in an event of simultaneous detection of multiple events by the power supply controller [col. 5-15: “Thus as seen in the embodiment of FIG. 3 all resume signals (such as interrupts) are routed to the smallest available core, which determines whether it can handle the resume operation, or instead is to send a wake signal to a larger core to continue. ”].
As to claim 14,
Hendrich teaches the computer system is a microcontroller [col. 11, line 58-66: “chipset 690 includes an interface 692 to couple chipset 690 with a high-performance graphics engine 638, by a P-P interconnect 639. In turn, chipset 690 may be coupled to a first bus 616 via an interface 696. As shown in FIG. 11, various input/output (I/O) devices 614 may be coupled to first bus 616, along with a bus bridge 618 which couples first bus 616 to a second bus 620. Various devices may be coupled to second bus 620 including, for example, a keyboard/mouse 622, communication devices 626 and a data storage unit 628 such as a disk drive or other mass storage device which may include code 630, in one embodiment. Further, an audio I/O 624 may be coupled to second bus 620. Embodiments can be incorporated into other types of systems including mobile devices such as a smart cellular telephone, tablet computer, netbook, or so forth.”].
As to claim 15-16,
Hendrich anticipates the claim according to the reasoning set forth in the claim 10-11 supra.
As to claim 22,
Hendrich teaches the at least one event comprises an interrupt request [“PCU 450 may include an interrupt history storage 456. Such storage may include a plurality of entries each identifying an interrupt that has occurred during system operation and whether the interrupt was successfully handled by the small core. Then based on this history, when a given interrupt is received, a corresponding entry of this storage can be accessed to determine whether a previous interrupt of the same type was successfully handled by the small core. If so, the PCU can direct the new incoming interrupt to the same small core. Instead, if it is determined based on this history that this type of interrupt was not successfully handled by small core (or with unsatisfactorily low performance), the interrupt can instead be sent to a large core.”].
As to claim 23,
Hendrick teaches initializing the computer system comprises: initializing the computer system in terms of security and clocks [“Referring now to FIG. 9, shown is a timing diagram illustrating operations occurring in a large core 710 and a small core 720 in accordance with an embodiment of the present invention. As seen, a longer sleep duration for large core 710 can be enabled by allowing a device interrupt to be provided to small core 720 directly, and determining in the small core whether it can handle the interrupt. If so, large core 710 can remain in a sleep state and the interrupt handled on small core 720.”].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hendrich [10664039], in view of Talla [20100325391]
As to claim 12,
Hendrich teaches one of the at least two processors that is powered on by the activation of the power supply. But do not explicitly teach one of the at least two processors are configured to initialize the computer system
However, Talla [20100325391] teaches one of the at least two processors is configured to initialize the computer system [0004: “In a multi-core system, multiple cores may be utilizing a shared resource. However, internal resources common to the shared resource may need to be initialized by only one core, and independent and uncoordinated initialization by multiple cores may cause errors”]
It would have been obvious to person of ordinary skill in the art before the effective filing of the claimed invention to combine teaching of Hendrich and Tall because both are directed toward multiple cores. Furthermore, Talla improves upon Hendrich by being able to initializing computer by the one of the multiple cores in order to avoid errors)
As to claim 17,
Combination of Hendrich and Talla teach this claim according to the reasoning set forth in claim 12 supra.
Allowable Subject Matter
Claim 13 and 18-21 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Muckle [ 20160026507] teaches [0029: “task characterization module 240 may characterize a task as a small task or a non-small task” 0029: “if a task is a “small task” it is small with respect to every CPU because for a task to be small, it must be below a certain percentage of the smallest CPU in the system. Normally it is desirable to wake a task on an idle CPU to minimize the latency for it to execute, which may mean waking the idle CPU up out of a deep power-saving state.”]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KESHAB R PANDEY whose telephone number is (571)270-0176. The examiner can normally be reached Monday-Friday 9:00-5:00(ET).
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/KESHAB R PANDEY/Primary Examiner, Art Unit 2176