DETAILED ACTION
The instant application having Application No. 18/832,468 has a total of 12 claims pending in the application; there are 2 independent claims and 10 dependent claims, all of which are ready for examination by the examiner.
Action Superseding Prior Action
This Office action replaces the Office action mailed on October 22, 2025. It corrects the omission of claims 12-20 and addresses claims 12-20 on the merits, and supersedes the prior action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
INFORMATION CONCERNING THE SPECIFICATION
Specification
The applicant’s specification submitted is acceptable for examination purposes.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 12 are rejected under 35 U.S.C. 101 because the Applicant has provided evidence that the Applicant intends the term "computer-readable storage medium” to include non-statutory matter. The Applicant describes a computer-readable storage medium as including open ended language and thus it is reasonable to interpret it to include all possible mediums, including non-statutory mediums (see paragraph 0161). The words "storage" and/or "recording" are insufficient to convey only statutory embodiments to one of ordinary skill in the art absent an explicit and deliberate limiting definition or clear differentiation between storage media and transitory media in the disclosure. As such, the claim is drawn to a form of energy. Energy is not one of the four categories of invention and therefore this/these claim(s) is/are not statutory. Energy is not a series of steps or acts and thus is not a process. Energy is not a physical article or object and as such is not a machine or manufacture. Energy is not a combination of substances and therefore not a composition of matter.
The Examiner suggests amending the claim to read as a -non-transitory machine-readable storage medium–.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 1-2 and 7-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Pillai et al. (Publication Number US 2023/0086027 A1) in view of Pan (Publication Number US 2021/0256105 A1).
As per claim 1, Pillai et al. discloses “A data processing system, comprising: a server and an intelligence board, wherein the server is connected to the intelligence board through a peripheral component interface express (PCIE) physical connection (PCIe card with SPI 308 that connect top a host system through PCIe signal 324; FIG. 3).”
Pillai et al. discloses “wherein, the server is configured to control power-on of the intelligence board through a sequential control circuit (where the PCIe card may be powered through the power rails; Paragraphs 0030 and 0033).” Pillai et al. discloses “wherein the intelligence board is configured to acquire the target data that is sent by the server through the SPI and transmitted through the PCIE physical connection, [and perform trusted measurement on the target data to obtain a measurement result] (where FW loading is done via SPI 308, with a status signal sent to the PCIe processor 312 once the SOC device is done with its internal setup [Paragraph 0033], indicating that operations done through SPI have status information sent through PCIe).” Pillai et al. discloses “wherein the server is configured to switch the SPI to the PCIE when the measurement result indicates that the server is trusted, and perform data transmission through the PCIE (where FW loading is done via SPI 308, with a status signal sent to the PCIe processor 312 once the SOC device is done with its internal setup [Paragraph 0033], indicating that operations done through SPI have status information sent through PCIe).”
However, Pillai et al. does not disclose measurement for a trusted environment as disclosed in the limitations “and perform trusted measurement on the target data to obtain a measurement result,” “and a serial peripheral interface (SPI) bus is built in the server,” and “the intelligence board is configured to switch a PCIE interface module of the intelligence board to an SPI trusted measurement interface module of the intelligence board under a power-on and trustable circumstance, and the SPI trusted measurement interface module is configured to request for target data to be measured from the server through the PCIE physical connection.”
Pan discloses measurement for a trusted environment as disclosed in the limitations “and perform trusted measurement on the target data to obtain a measurement result (steps S102 and S103; FIG. 1).”
Pan discloses “and a serial peripheral interface (SPI) bus is built in the server (through a verification center which communicates with the first trusted computing chip through SPI while communicating with the second trusted computing chip through PCIe [Paragraphs 0035 and 0070] with the first computing chip used at startup with the second computing chip used after start up [Paragraph 0073]. Note that Pan is directed to the measurement for a trusted environment with Pillai et al. directed to primary access to a SPI environment through PCIe in [FIG. 3; Paragraph 0033]).”
Pan discloses “the intelligence board is configured to switch a PCIE interface module of the intelligence board to an SPI trusted measurement interface module of the intelligence board under a power-on and trustable circumstance, and the SPI trusted measurement interface module is configured to request for target data to be measured from the server through the PCIE physical connection (through a verification center which communicates with the first trusted computing chip through SPI while communicating with the second trusted computing chip through PCIe [Paragraphs 0035 and 0070] with the first computing chip used at startup with the second computing chip used after start up [Paragraph 0073]. Note that Pan is directed to the measurement for a trusted environment with Pillai et al. directed to primary access to a SPI environment through PCIe in [FIG. 3; Paragraph 0033]).”
Pillai et al. and Pan are analogous art in that they in the field of device connections through the use of SPI and PCIe.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Pillai et al. and Pan to enable high reliability of trusted computing for dynamic measurements [Paragraph 0003].
As per claim 2, Pillai et al. discloses “The system according of claim 1 (as disclosed by Pillai et al. and Pan above), wherein the server comprises: an SPI on-off switching module, configured to switch the SPI to the PCIE physical connection (where FW loading is done via SPI 308, with a status signal sent to the PCIe processor 312 once the SOC device is done with its internal setup [Paragraph 0033], indicating that operations done through SPI have status information sent through PCIe).”
As per claim 7, Pillai et al. discloses “The system according of claim 1 (as disclosed by Pillai et al. and Pan above), wherein the server comprises: a PCIE on-off switching module, configured to switch the SPI to the PCIE (where FW loading is done via SPI 308, with a status signal sent to the PCIe processor 312 once the SOC device is done with its internal setup [Paragraph 0033], indicating that operations done through SPI have status information sent through PCIe).”
As per claim 8, Pillai et al. discloses “The system according of claim 1 (as disclosed by Pillai et al. and Pan above), wherein the intelligence board comprises: an interface switching module, configured to switch the PCIE interface module to the SPI trusted measurement interface module (where FW loading is done via SPI 308, with a status signal sent to the PCIe processor 312 once the SOC device is done with its internal setup [Paragraph 0033], indicating that operations done through SPI have status information sent through PCIe).”
As per claim 9, Pillai et al. discloses “The system according of claim 8 (as disclosed by Pillai et al. and Pan above), wherein the interface switching module is further configured to switch the SPI trusted measurement interface module to the PCIE interface module, after the measurement result is obtained by performing the trusted measurement on the target data (where FW loading is done via SPI 308, with a status signal sent to the PCIe processor 312 once the SOC device is done with its internal setup [Paragraph 0033], indicating that operations done through SPI have status information sent through PCIe).”
As per claim 10, Pan discloses “The system according to any one of claims 1 to 9 (as disclosed by Pillai et al. and Pan above), wherein the intelligence board comprises: a trusted platform control module (TPCM), configured to perform the trusted measurement on an operating system of the intelligence board, wherein a trusted operating system is configured to perform the trusted measurement on the target data to obtain the measurement result (through a verification center which communicates with the first trusted computing chip through SPI while communicating with the second trusted computing chip through PCIe [Paragraphs 0035 and 0070] with the first computing chip used at startup with the second computing chip used after start up [Paragraph 0073]. Note that Pan is directed to the measurement for a trusted environment with Pillai et al. directed to primary access to a SPI environment through PCIe in [FIG. 3; Paragraph 0033]).”
As per claim 11, Pillai et al. discloses “A data processing method, comprising: in response to an intelligence board being powered on [and trusted] (where the PCIe card may be powered through the power rails; Paragraphs 0030 and 0033), switching a PCIE interface module of the intelligence board to an SPI trusted measurement interface module of the intelligence board (where FW loading is done via SPI 308, with a status signal sent to the PCIe processor 312 once the SOC device is done with its internal setup [Paragraph 0033], indicating that operations done through SPI have status information sent through PCIe).”
Pillai et al. discloses “acquiring the target data that is sent by the server through a built-in serial peripheral interface bus (SPI) and transmitted through the PCIE physical connection (where FW loading is done via SPI 308, with a status signal sent to the PCIe processor 312 once the SOC device is done with its internal setup [Paragraph 0033], indicating that operations done through SPI have status information sent through PCIe).”
However, Pillai et al. does not disclose measurement for a trusted environment as disclosed in the limitations “wherein the SPI trusted measurement interface module is configured to request for target data to be measured from a server through a PCIE physical connection” and “performing trusted measurement on the target data to obtain a measurement result, wherein when the measurement result indicates that the server is trusted, the SPI is switched to the PCIE by the server, and the server performs data transmission through the PCIE.”
Pan discloses measurement for a trusted environment as disclosed in the limitations “wherein the SPI trusted measurement interface module is configured to request for target data to be measured from a server through a PCIE physical connection (steps S102 and S103; FIG. 1).” Pan discloses “performing trusted measurement on the target data to obtain a measurement result, wherein when the measurement result indicates that the server is trusted, the SPI is switched to the PCIE by the server, and the server performs data transmission through the PCIE (through a verification center which communicates with the first trusted computing chip through SPI while communicating with the second trusted computing chip through PCIe [Paragraphs 0035 and 0070] with the first computing chip used at startup with the second computing chip used after start up [Paragraph 0073]. Note that Pan is directed to the measurement for a trusted environment with Pillai et al. directed to primary access to a SPI environment through PCIe in [FIG. 3; Paragraph 0033]).”
Pillai et al. and Pan are analogous art in that they in the field of device connections through the use of SPI and PCIe.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Pillai et al. and Pan to enable high reliability of trusted computing for dynamic measurements [Paragraph 0003].
As per claim 12, Pillai et al. discloses “A non-transitory computer-readable storage medium, comprising a program stored thereon, wherein the program, when running by a processor, controls a device in which the computer-readable storage medium is located to execute the following: in response to an intelligence board being powered on and trusted (where the PCIe card may be powered through the power rails; Paragraphs 0030 and 0033), switching a peripheral component interface express (PCIE) interface module of the intelligence board to a serial peripheral interface (SPI) bus trusted measurement interface module of the intelligence board (where FW loading is done via SPI 308, with a status signal sent to the PCIe processor 312 once the SOC device is done with its internal setup [Paragraph 0033], indicating that operations done through SPI have status information sent through PCIe).”
Pillai et al. discloses “acquiring the target data that is sent by the server through a built-in serial peripheral interface (SPI) bus and transmitted through the PCIE physical connection (where FW loading is done via SPI 308, with a status signal sent to the PCIe processor 312 once the SOC device is done with its internal setup [Paragraph 0033], indicating that operations done through SPI have status information sent through PCIe).”
However, Pillai et al. does not disclose measurement for a trusted environment as disclosed in the limitations “wherein the SPI trusted measurement interface module is configured to request for target data to be measured from a server through a PCIE physical connection” and “performing trusted measurement on the target data to obtain a measurement result, wherein when the measurement result indicates that the server is trusted, the SPI is switched to the PCIE by the server, and the server performs data transmission through the PCIE.”
Pan discloses measurement for a trusted environment as disclosed in the limitations “wherein the SPI trusted measurement interface module is configured to request for target data to be measured from a server through a PCIE physical connection (through a verification center which communicates with the first trusted computing chip through SPI while communicating with the second trusted computing chip through PCIe [Paragraphs 0035 and 0070] with the first computing chip used at startup with the second computing chip used after start up [Paragraph 0073]. Note that Pan is directed to the measurement for a trusted environment with Pillai et al. directed to primary access to a SPI environment through PCIe in [FIG. 3; Paragraph 0033]).” Pan discloses “performing trusted measurement on the target data to obtain a measurement result (steps S102 and S103; FIG. 1), wherein when the measurement result indicates that the server is trusted, the SPI is switched to the PCIE by the server, and the server performs data transmission through the PCIE (through a verification center which communicates with the first trusted computing chip through SPI while communicating with the second trusted computing chip through PCIe [Paragraphs 0035 and 0070] with the first computing chip used at startup with the second computing chip used after start up [Paragraph 0073]. Note that Pan is directed to the measurement for a trusted environment with Pillai et al. directed to primary access to a SPI environment through PCIe in [FIG. 3; Paragraph 0033]).”
Pan discloses “wherein the SPI trusted measurement interface module is configured to request for target data to be measured from a server through a PCIE physical connection (through a verification center which communicates with the first trusted computing chip through SPI while communicating with the second trusted computing chip through PCIe [Paragraphs 0035 and 0070] with the first computing chip used at startup with the second computing chip used after start up [Paragraph 0073]. Note that Pan is directed to the measurement for a trusted environment with Pillai et al. directed to primary access to a SPI environment through PCIe in [FIG. 3; Paragraph 0033]).”
Pillai et al. and Pan are analogous art in that they in the field of device connections through the use of SPI and PCIe.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Pillai et al. and Pan to enable high reliability of trusted computing for dynamic measurements [Paragraph 0003].
As per claim 13, Pan discloses “The system according of claim 2 (as disclosed by Pillai et al. and Pan above), wherein the intelligence board comprises: a trusted platform control module (TPCM), configured to perform the trusted measurement on an operating system of the intelligence board, wherein a trusted operating system is configured to perform the trusted measurement on the target data to obtain the measurement result (through a verification center which communicates with the first trusted computing chip through SPI while communicating with the second trusted computing chip through PCIe [Paragraphs 0035 and 0070] with the first computing chip used at startup with the second computing chip used after start up [Paragraph 0073]. Note that Pan is directed to the measurement for a trusted environment with Pillai et al. directed to primary access to a SPI environment through PCIe in [FIG. 3; Paragraph 0033]).”
As per claim 14, Pan discloses “The system according of claim 3 (as disclosed by Pillai et al. and Pan above), wherein the intelligence board comprises: a trusted platform control module (TPCM), configured to perform the trusted measurement on an operating system of the intelligence board, wherein a trusted operating system is configured to perform the trusted measurement on the target data to obtain the measurement result (through a verification center which communicates with the first trusted computing chip through SPI while communicating with the second trusted computing chip through PCIe [Paragraphs 0035 and 0070] with the first computing chip used at startup with the second computing chip used after start up [Paragraph 0073]. Note that Pan is directed to the measurement for a trusted environment with Pillai et al. directed to primary access to a SPI environment through PCIe in [FIG. 3; Paragraph 0033]).”
As per claim 15, Pan discloses “The system according of claim 4 (as disclosed by Pillai et al. and Pan above), wherein the intelligence board comprises: a trusted platform control module (TPCM), configured to perform the trusted measurement on an operating system of the intelligence board, wherein a trusted operating system is configured to perform the trusted measurement on the target data to obtain the measurement result (through a verification center which communicates with the first trusted computing chip through SPI while communicating with the second trusted computing chip through PCIe [Paragraphs 0035 and 0070] with the first computing chip used at startup with the second computing chip used after start up [Paragraph 0073]. Note that Pan is directed to the measurement for a trusted environment with Pillai et al. directed to primary access to a SPI environment through PCIe in [FIG. 3; Paragraph 0033]).”
As per claim 16, Pan discloses “The system according of claim 5 (as disclosed by Pillai et al. and Pan above), wherein the intelligence board comprises: a trusted platform control module (TPCM), configured to perform the trusted measurement on an operating system of the intelligence board, wherein a trusted operating system is configured to perform the trusted measurement on the target data to obtain the measurement result (through a verification center which communicates with the first trusted computing chip through SPI while communicating with the second trusted computing chip through PCIe [Paragraphs 0035 and 0070] with the first computing chip used at startup with the second computing chip used after start up [Paragraph 0073]. Note that Pan is directed to the measurement for a trusted environment with Pillai et al. directed to primary access to a SPI environment through PCIe in [FIG. 3; Paragraph 0033]).”
As per claim 17, Pan discloses “The method according of claim 11 (as disclosed by Pillai et al. and Pan above), wherein the method further comprises: switching the SPI trusted measurement interface module to the PCIE interface module, after the measurement result is obtained by performing the trusted measurement on the target data (through a verification center which communicates with the first trusted computing chip through SPI while communicating with the second trusted computing chip through PCIe [Paragraphs 0035 and 0070] with the first computing chip used at startup with the second computing chip used after start up [Paragraph 0073]. Note that Pan is directed to the measurement for a trusted environment with Pillai et al. directed to primary access to a SPI environment through PCIe in [FIG. 3; Paragraph 0033]).”
As per claim 18, Pan discloses “The method according of claim 11 (as disclosed by Pillai et al. and Pan above), wherein the method further comprises: performing the trusted measurement on an operating system of the intelligence board, wherein a trusted operating system is used to perform the trusted measurement on the target data to obtain the measurement result (through a verification center which communicates with the first trusted computing chip through SPI while communicating with the second trusted computing chip through PCIe [Paragraphs 0035 and 0070] with the first computing chip used at startup with the second computing chip used after start up [Paragraph 0073]. Note that Pan is directed to the measurement for a trusted environment with Pillai et al. directed to primary access to a SPI environment through PCIe in [FIG. 3; Paragraph 0033]).”
As per claim 19, Pan discloses “The storage medium according of claim 12 (as disclosed by Pillai et al. and Pan above), wherein the device is further controlled to execute the following: switching the SPI trusted measurement interface module to the PCIE interface module, after the measurement result is obtained by performing the trusted measurement on the target data (through a verification center which communicates with the first trusted computing chip through SPI while communicating with the second trusted computing chip through PCIe [Paragraphs 0035 and 0070] with the first computing chip used at startup with the second computing chip used after start up [Paragraph 0073]. Note that Pan is directed to the measurement for a trusted environment with Pillai et al. directed to primary access to a SPI environment through PCIe in [FIG. 3; Paragraph 0033]).”
As per claim 20, Pan discloses “The storage medium according of claim 12 (as disclosed by Pillai et al. and Pan above), wherein the device is further controlled to execute the following: performing the trusted measurement on an operating system of the intelligence board, wherein a trusted operating system is used to perform the trusted measurement on the target data to obtain the measurement result (through a verification center which communicates with the first trusted computing chip through SPI while communicating with the second trusted computing chip through PCIe [Paragraphs 0035 and 0070] with the first computing chip used at startup with the second computing chip used after start up [Paragraph 0073]. Note that Pan is directed to the measurement for a trusted environment with Pillai et al. directed to primary access to a SPI environment through PCIe in [FIG. 3; Paragraph 0033]).”
Claims 3-6 are rejected under 35 U.S.C. 103(a) as being unpatentable over Pillai et al. (Publication Number US 2023/0086027 A1) and Pan (Publication Number US 2021/0256205 A1) in view of Edwards et al. (Publication Number US 2022/0043914 A1).
As per claim 3, Pillai et al. and Pan discloses “The system according of claim 2 (as disclosed by Pillai et al. and Pan above).” While Pan discloses “after the measurement result is obtained by the intelligence board through performing the trusted measurement on the target data (through a verification center which communicates with the first trusted computing chip through SPI while communicating with the second trusted computing chip through PCIe [Paragraphs 0035 and 0070] with the first computing chip used at startup with the second computing chip used after start up; Paragraph 0073),” Pillai et al. and Pan do not disclose the use of a BMC in a trusted environment as disclosed in the limitation “wherein the server comprises: a sequential control module, configured to control the SPI on-off switching module to switch the SPI to a baseboard management controller (BMC) and a central processing unit (CPU) of the server.”
Edwards et al. discloses the use of a BMC in a trusted environment as disclosed in the limitation “wherein the server comprises: a sequential control module, configured to control the SPI on-off switching module to switch the SPI to a baseboard management controller (BMC) and a central processing unit (CPU) of the server (the SPI switch 124 may be in the bus that is used to access read-only memory (ROM). The SPI switch 124 may enable the BMC 116 to check if the general-purpose processor 108 is loading the correct firmware. For example, the SPI switch 124 may enable the BMC 116 to read the basic input output system (BIOS) 126, before the BIOS 126 is loadable by the processor 108. If the BIOS 126 is correct, the BMC 116 may flip the switch to allow the processor 108 to load the BIOS 126. The SPI switch 124 may also enable the BMC 116 to restore or update BIOS 126; Paragraph 0020; FIG. 1).”
Pillai et al., Pan, and Edwards et al. are analogous art in that they in the field of device connections through the use of SPI and PCIe.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Pillai et al. and Pan with elements of Edwards et al. to lessen potential attack vectors in systems with multiple components [Paragraph 0001].
As per claim 4, Edwards et al. discloses “The system according of claim 3 (as disclosed by Pillai et al., Pan, and Edwards et al. above), wherein the SPI on-off switching module is configured to control, based on the SPI, the BMC to access data in a first memory BMC Flash of the server (For example, the SPI switch 124 may enable the BMC 116 to read the basic input output system (BIOS) 126, before the BIOS 126 is loadable by the processor 108; Paragraph 0020; FIG. 1), and control, based on the SPI, the CPU to access data in a second memory Boot Rom of the server (if the BIOS 126 is correct, the BMC 116 may flip the switch to allow the processor 108 to load the BIOS 126. The SPI switch 124 may also enable the BMC 116 to restore or update BIOS 126; Paragraph 0020; FIG. 1).”
As per claim 5, Edwards et al. discloses “The system according of claim 4 (as disclosed by Pillai et al., Pan, and Edwards et al. above), wherein the BMC is configured to start based on the data in the BMC Flash, the started BMC Flash is configured to control the CPU to start based on the data in the Boot Rom, and the started CPU is configured to control an operating system of the server to start, to control the PCIE for data transmission (the SPI switch 124 may be in the bus that is used to access read-only memory (ROM). The SPI switch 124 may enable the BMC 116 to check if the general-purpose processor 108 is loading the correct firmware. For example, the SPI switch 124 may enable the BMC 116 to read the basic input output system (BIOS) 126, before the BIOS 126 is loadable by the processor 108. If the BIOS 126 is correct, the BMC 116 may flip the switch to allow the processor 108 to load the BIOS 126. The SPI switch 124 may also enable the BMC 116 to restore or update BIOS 126; Paragraph 0020; FIG. 1).”
As per claim 6, Edwards et al. discloses “The system according of claim 4 (as disclosed by Pillai et al., Pan, and Edwards et al. above), wherein the target data comprises the data in the BMC Flash and the data in the Boot Rom (see the BIOS 126; Paragraph 0020; FIG. 1).”
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(c), the applicant's submission of the Information Disclosure Statement dated July 23, 2024, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
The following references teach trusted environment operations.
U.S. PATENT NUMBERS:2014/0068275 A1 –BMC with SPI bus [FIG. 1]
2018/0088962 A1 – use of BMC within a trusted environment (note the word “watchdog”) [Abstract; FIG. 2]
2021/0192050 A1 – [Abstract]
2022/0067165 A1 – [Paragraph 0048; FIG. 1-3]
CLOSING COMMENTS
Conclusion
The examiner requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Yu whose telephone number is (571)272-9779. The examiner can normally be reached Monday - Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS ALROBAYE can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/H.W.Y/Examiner, Art Unit 2181 January 15, 2026
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181