DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner’s Notes
There seems to be a possible allowability agreement in claim 13 if Applicant excludes the DC supply lines from being disposed in the layer as the first and second wire. In other words, the first and second DC power supply lines are being disposed in the same layer as the third metal wire but not disposed in the layer as the first and second wire. This language is only used for discussion purposes and not an amendment proposition.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 lacks antecedent basis for including the language “the first DC power supply line and the second DC power supply line.” However, preceding claims 1 and 12 do not refer to any DC power supply lines. This language is included in other claims, however, not in the claim branch of claim 13.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-9, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Masleid et al (Publication number: US 2014/0169117) in view of Miyaoka et al (Patent number: US 5,220,187).
Consider Claim 1, Masleid et al shows a decoder circuit (see figure 2); (Read as pre-decode stage 208 in addition to decode stage 210), comprising:
(a) A plurality of logic circuit groups arranged sequentially along a first direction connected in series; each of the logic circuit groups comprising: a plurality of logic circuits arranged sequentially along a second direction and connected in series, the second direction being intersected with the first direction (see figure 2); (The arrangement of the logic circuit groups in figure 2 is equivalent to the arrangement of logic circuit groups depicted in figure 5 of the instant application).
(b) Each of the logic circuits comprising: at least one N-type transistor and at least one P-type transistor (see figures 2, and 2A-2B; and paragraph 42); (transistors 302 and 304 are P-type, and transistors 308 and 306 are N-type).
(c) Wherein in each of the logic circuit groups, N-type transistors in the plurality of logic circuits are arranged sequentially along the second direction, P-type transistors in the plurality of logic circuits are arranged sequentially along the second direction, a set of the P-type transistors and a set of the N-type transistors are arranged sequentially along the first direction (see figures 2 and 3A-3B; paragraphs 42 and 43); ( The example two-high NOR gate 216 in the example of FIG. 3A includes two p-type Field Effect Transistors (PFETs) 302, 304 coupled in series. The example two-high NOR gate also includes two n-type FETs (NFETs) 308, 306 coupled in parallel. The example two-high NAND gate 218 of FIG. 3B includes two PFETs 310, 312 coupled in parallel. The example two-high NAND gate 218 of FIG. 3B also includes two NFETs 314, 316 coupled in series. The PFET 310 and NFET 316 receive a signal from a 1H4 bus, such as bus 206a depicted in FIG. 2).
(d) And a distance between a channel region of a P-type transistor and a channel region of a N-type transistor adjacent to the P-type transistor in the first direction is greater than a distance between channel regions of two adjacent transistors and N-type transistors in each of the set of the P-type transistors and the set of the N-type transistors (see figure 2); (see the distance between the NAND gates 218 and NOR gates 216. The term “adjacent” applies to transistors being adjacent to each other in a vertical or a horizontal direction).
However, Masleid et al does not specifically show that each of the at least one N-type transistor and the at least one P-type transistor has a channel region and two substrate isolation regions, the two substrate isolation regions being respectively disposed on two sides of the channel region in the first direction, and each of the substrate isolation regions is provided with a plurality of vias arranged sequentially along the second direction.
In related art, Miyaoka et al shows each of the at least one N-type transistor and the at least one P-type transistor has a channel region and two substrate isolation regions, the two substrate isolation regions being respectively disposed on two sides of the channel region in the first direction, and each of the substrate isolation regions is provided with a plurality of vias arranged sequentially along the second direction (see figure 2; column 4, lines 28-60; column 17, lines 55-60); (Each of the NMOS regions NM1-NM3 includes three N-channel MOSFETs each of which is endowed with a comparatively high conductance, and the NMOS region NM4 includes three N-channel MOSFETs each of which is endowed with a comparatively low conductance. In each basic cell BC, gates G made of polycrystalline silicon. These gates G are extended between the sources S and drains D of the corresponding N-channel MOSFETs of the NMOS region NM1. Thus, the gates of the individual P-channel MOSFETs of the PMOS region PM1 and the corresponding N-channel MOSFETs of the NMOS region NM1 are respectively coupled in common. The P-type isolation regions 102 and 102' can be formed in the substrate 100 by diffusion of boron into the substrate, while the buried layer regions 101, 101' and 101" can be formed by diffusion of antimony into the substrate).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the isolation regions of Miyaoka et al into the decoder structure of Masleid et al in order to shorten the manufacturing process (see Miyaoka et al; column 9, lines 45-57).
Consider Claim 2, Miyaoka et al shows that each two adjacent logic circuit groups are arranged in mirror symmetry along an axis extending in the second direction (see column 15, lines 60-67; column 16, lines 1-20); (The basic cells BC1 and BC2 are held in mirror symmetry with respect to a two-dot chain line X drawn in the figure. As a result, the bipolar transistors B1, B2 in the basic cell BC1 and bipolar transistors B3, B4 in the basic cell BC2 are arranged in proximity. Further, the basic cells BC1, BC2 and those BC3, BC4 are held in mirror symmetry with respect to a two-dot chain line).
Consider Claim 3 and 17, Miyaoka et al shows that in each two adjacent logic circuit groups, transistors disposed on two sides of the axis share the one substrate isolation region which is between the two adjacent logic circuit groups (See figure 2; column 4, lines 28-60; column 17, lines 55-60); (Each of the NMOS regions NM1-NM3 includes three N-channel MOSFETs. The P-type isolation regions 102 and 102' can be formed in the substrate 100 by diffusion of boron into the substrate, while the buried layer regions 101, 101' and 101" can be formed by diffusion of antimony into the substrate).
Consider Claim 7, Miyaoka et al shows that an area of the substrate isolation region of the P-type transistor is greater than an area the substrate isolation region of the N-type transistor (see figure 10; column 15, lines 60-67; column 16, lines 1-20); (see the P and N regions shown in figure 10).
Consider Claim 8, Miyaoka et al shows that in each of the logic circuits, substrate isolation regions of P-type transistors disposed on the same side of channel regions of the P-type transistors are connected and flush in the second direction, and the channel regions of the P-type transistors are spaced apart from each other and edges of at least one side of the channel regions are flush in the second direction; and substrate isolation regions of N-type transistors disposed on the same side of channel regions of the N-type transistors are connected and flush in the second direction, and the channel regions of the N-type transistors are spaced apart from each other and edges of at least one side of the channel regions are flush in the second direction (see figure 10; column 15, lines 60-67; column 16, lines 1-20); (The channel regions of P-type transistor shown in figure 10 are connected and flush in the second direction; and the N-type transistors are spaced apart from each other and edges of at least one side of the channel regions are flush in the second direction).
Consider Claim 9, Miyaoka et al shows that each of the at least one N-type transistor and the at least one P-type transistor has a gate layer and a source-drain metal layer which are rectangular in a top view; and the gate layer and the source-drain metal layer overlap with each other, a length direction of the gate layer extends along the first direction, and a length direction of the source- drain metal layer extends along the second direction; wherein the channel region overlaps with an overlapping region of the gate layer and the source-drain metal layer (see figure 5; and column 6, line 60-67; and column 7, lines 1-10); (The CMOS NAND gate circuit NAG1 includes a P-channel MOSFET Q2 and N-channel MOSFETs Q12-Q14 whose source-drain paths are provided in a series form across the power supply voltage V.sub.cc and ground potential GND of the circuitry. The source-drain path of the MOSFET Q2 is further provided with the source-drain paths of P-channel MOSFETs Q3 and Q4 in a parallel form).
Consider Claim 15, Masleid et al shows a panel driving circuit and a display panel, the panel driving circuit being connected to the display panel and being configured to drive the display panel to display; wherein the panel driving circuit comprises the decoder circuit according claim 1 (see figure 2; and paragraphs 19-21).
Consider Claim 16, Miyaoka et al shows that each two adjacent logic circuit groups are arranged in mirror symmetry along an axis extending in the second direction (see column 15, lines 60-67; column 16, lines 1-20); (The basic cells BC1 and BC2 are held in mirror symmetry with respect to a two-dot chain line X drawn in the figure. As a result, the bipolar transistors B1, B2 in the basic cell BC1 and bipolar transistors B3, B4 in the basic cell BC2 are arranged in proximity. Further, the basic cells BC1, BC2 and those BC3, BC4 are held in mirror symmetry with respect to a two-dot chain line).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Masleid et al (Publication number: US 2014/0169117) in view of Miyaoka et al (Patent number: US 5,220,187) in view of Kim et al (Publication number: US 2021/0382511).
Consider Claim 10, Masleid et al in view of Miyaoka et al do not specifically show that each of the logic circuits is further respectively connected to a first DC power supply line and a second DC power supply line and is configured to perform logic processing based on a signal provided by the first DC power supply line and a signal provided by the second DC power supply line.
In related art, Kim et al shows that each of the logic circuits is further respectively connected to a first DC power supply line and a second DC power supply line and is configured to perform logic processing based on a signal provided by the first DC power supply line and a signal provided by the second DC power supply line (see figure 1; and paragraphs 15-16); (Microelectronic device 100 can include a main circuit 102 and a DC power supply circuit 110. Main circuit 102 can be powered by a DC voltage-regulated supply current and includes multiple sub-circuits 104. Each sub-circuit of multiple sub-circuits 104 can receive a sub-circuit activation signal and can be active or inactive according to the received sub-circuit activation signal).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the DC power supply circuit of Kim et al into the teaching of Masleid et al and Miyaoka et al in order to regulate the voltage for power efficiency (see Kim et al; paragraphs 1-2, and 15-16).
Consider Claim 11, Kim et al shows that the first DC power supply line and the second DC power supply line are respectively disposed on two sides of the plurality of logic circuit groups in the second direction and both extend along the first direction, and the width of the first DC power supply line in the second direction is equal to the width of the second DC power supply line in the second direction (see the DC power circuit 110 and main circuit 102 in figure 1).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Masleid et al (Publication number: US 2014/0169117) in view of Miyaoka et al (Patent number: US 5,220,187) in view of Kim et al (Publication number: US 2016/0300839).
Consider Claim 12, Masleid et al in view of Miyaoka et al do not specifically show that the decoder circuit is disposed on one side of a substrate, at least a part of connections in the decoder circuit, is realized by a plurality of layers of metal wires stacked sequentially in a direction away from the substrate, each two adjacent layers of metal wires are connected with each other through a via hole.
In related art, Kim et al shows that the decoder circuit is disposed on one side of a substrate, at least a part of connections in the decoder circuit, is realized by a plurality of layers of metal wires stacked sequentially in a direction away from the substrate, each two adjacent layers of metal wires are connected with each other through a via hole (see figures 2 and 6; also paragraphs 31-33, and 4042); (The contacts CB may be disposed on some regions of the first through third conductive lines CL1 through CL3 between the first and second active regions AR1 and AR2. Here, the contacts CB may be referred to as gate contacts, gate contact patterns, or gate contact plugs. In detail, a first upper contact CB la may be disposed on the first upper conductive line CL1a, a first lower contact CB1b may be disposed on the third lower conductive line CL3b, a second upper contact CB2a may be disposed on the second upper conductive line CL2a, and a second lower contact CB2b may be disposed on the second lower conductive line CL2b).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the conductive line structure of Kim et al into the decoder circuit of Masleid and Miyaoka in order to utilize different control signals (see Kim et al; paragraphs 42 and 43).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Masleid et al (Publication number: US 2014/0169117) in view of Miyaoka et al (Patent number: US 5,220,187) in view of Kim et al (Publication number: US 2016/0300839) in view of Kim et al’ (Publication number: US 2021/0382511).
Consider Claim 13, Masleid, Miyaoka, and Kim show that at least a part of connections in the decoder circuit is realized by a total of three layers of metal wires comprising a first metal wire, a second metal wire and a third metal wire which are sequentially stacked in the direction away from the substrate; wherein the first metal wire comprises a plurality of line segments extending along the first direction and a plurality of line segments extending along the second direction, the second metal wire comprises a plurality of line segments extending along the second direction, and the third metal wire comprises a plurality of line segments extending along the first direction (see figures 2 and 6; also paragraphs 31-33, and 4042); (The contacts CB may be disposed on some regions of the first through third conductive lines CL1 through CL3 between the first and second active regions AR1 and AR2. Here, the contacts CB may be referred to as gate contacts, gate contact patterns, or gate contact plugs. In detail, a first upper contact CB la may be disposed on the first upper conductive line CL1a, a first lower contact CB1b may be disposed on the third lower conductive line CL3b, a second upper contact CB2a may be disposed on the second upper conductive line CL2a, and a second lower contact CB2b may be disposed on the second lower conductive line CL2b).
However, Masleid, Miyaoka, and Kim do not specifically show that both the first DC power supply line and the second DC power supply line connected to each of the logic circuits are disposed in the same layer as the third metal wire.
In related art, Kim et al’ shows that both the first DC power supply line and the second DC power supply line connected to each of the logic circuits are disposed in the same layer as the third metal wire (see figure 1; and paragraphs 15-16); (Microelectronic device 100 can include a main circuit 102 and a DC power supply circuit 110. Main circuit 102 can be powered by a DC voltage-regulated supply current and includes multiple sub-circuits 104. Each sub-circuit of multiple sub-circuits 104 can receive a sub-circuit activation signal and can be active or inactive according to the received sub-circuit activation signal).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the DC power supply circuit of Kim et al’ into the teaching of Masleid et al and Miyaoka et al, and Kim et al in order to regulate the voltage for power efficiency (see Kim et al; paragraphs 1-2, and 15-16).
Allowable Subject Matter
Claims 4-6, 14, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL A FARAGALLA whose telephone number is (571)270-1107. The examiner can normally be reached Mon-Fri 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL A FARAGALLA/Primary Examiner, Art Unit 2624 03/20/2026