DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The references listed in the Information Disclosure Statement filed on 10/25/2024 have been considered by the examiner (see attached PTO-1449 forms).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JALADANKI et al. [US 2022/0271664 A1; hereinafter “JALADANKI”].
Regarding claim 1, JALADANKI teaches a circuit optimization method for a digital domain correction of a temperature sensor, comprising:
step 1: subjecting negative temperature coefficient voltages Vbep and Vben to a switch timing control (control signals 330, 340 and 350 for switches 325, 335 and 345 - 0041), thereby generating a corresponding negative temperature coefficient voltage Vbep (VMP 285, VMN 275 – 0040) and positive temperature coefficient voltage Dvbe (VMP 285, VMN 275 – 0040) as inputs into an operational transconductance amplifier (OTA) that serves as a core circuit of a Sigam-Delt analog-to-digital converter (ADC) (OTA 310 - figure 3 - 0040); and
step 2: generating, by a switch sampling circuit, Vintx by integrating; inputting the Vintx into a comparator (CMP) to acquire a final ADC output (ADC 365 – figure 3, 0040); and sending a feedback through a digital domain to an analog domain control switch logic (figure 3, 0041-0045).
Regarding claim 6, JALADANKI teaches a circuit optimization system for a digital domain correction of a temperature sensor, comprising:
a first module, configured to:
subject negative temperature coefficient voltages Vbep and Vben to a switch timing control (control signals 330, 340 and 350 for switches 325, 335 and 345 - 0041), thereby generating a corresponding negative temperature coefficient voltage Vbep (VMP 285, VMN 275 – 0040) and positive temperature coefficient voltage Dvbe (VMP 285, VMN 275 – 0040) as inputs into an OTA that serves as a core circuit of a Sigam-Delt ADC (OTA 310 - figure 3 - 0040); and
a second module, configured to:
generate, by a switch sampling circuit, Vintx by integrating;
input the Vintx into a CMP to acquire a final ADC output ADC 365 – figure 3, 0040); and
send a feedback through a digital domain to an analog domain control switch logic (figure 3, 0041-0045).
Allowable Subject Matter
Claims 2-5 and 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Relevant Prior Art / Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
LI et al. (US Patent Application Publication 2023/0067583 A1) discloses an analog-to-digital converter in operation with a thermopile array;
Peterson et al. (US Patent Application Publication 2021/0033654 A1) discloses a detector for measuring a resistance of a variable resistance sensor (VRS) that varies with respect to a time-varying stimulus.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICKY GO whose telephone number is (571)270-3340. The examiner can normally be reached on Monday through Friday from 9:00 a.m. to 5:30 p.m.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arleen M. Vazquez can be reached on (571) 272-2619. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RICKY GO/Primary Examiner, Art Unit 2857
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