Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to communications filed on 07/26/2024.
Claims 35-44 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/26/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 35 and 40 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Si (Pub. No.: US 2025/0240772 A1).
Regarding claim 35, Si teaches
A method performed by a terminal device (Si [0006] and [0030]: method by a terminal), the method comprising:
receiving first configuration information indicating that a sidelink transmission is based on interlace resource blocks (RBs) (Si [0112], [0005-0006], and claim 1: first configuration for sidelink transmission based on interlace of resource blocks);
receiving second configuration information indicating a first number of interlaces per a sub-channel within a resource pool (Si [0087], [0099], [0005-0006], and claim 2: second configuration configures a number of interlaces included in a sub-channel of the resource pool); and
performing the sidelink transmission on at least one sub-channel (Si [0075] and claims 6 and 13: sidelink transmission on a sub-channel).
Regarding claim 40, Si teaches
A terminal device, comprising a processor (Si [0045] and [0030]: a terminal device comprising a processor) configured to:
receive first configuration information indicating that a sidelink transmission is based on interlace resource blocks (RBs) (Si [0112], [0005-0006], and claim 1: first configuration for sidelink transmission based on interlace of resource blocks);
receive second configuration information indicating a first number of interlaces per a sub- channel within a resource pool (Si [0087], [0099], [0005-0006], and claim 2: second configuration configures a number of interlaces included in a sub-channel of the resource pool); and
perform the sidelink transmission on at least one sub-channel (Si [0075] and claims 6 and 13: sidelink transmission on a sub-channel).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 36-39 and 41-44 are rejected under 35 U.S.C. 103 as being unpatentable over Si (Pub. No.: US 2025/0240772 A1) in view of Miao (Pub. No.: US 2024/0340871 A1).
Regarding claim 36, Si teaches
The method of claim 35 (the limitations of parent claim 35 as indicated above),
Si further teaches
wherein the first number of interlaces are contiguous interlaces (Si [0095] and [0100]: number of interlaces being contiguous interlaces),
While Si does discuss sub-channel mapping to interlaces, Si does not explicitly disclose sub-channel #0 is mapped to interlace #0 to interlace # the first number-1, and sub-channel #1 is mapped to interlace # the first number to interlace # the first numberx2-1.
However, Miao, in the analogous art of sub-channels comprising interlaces, teaches
and sub-channel #0 is mapped to interlace #0 to interlace # the first number-1 (Miao [0079]: first sub-channel (sub-channel #0) with contiguous interlaces, mapped to interlace #0 to #2 which is the first number (3 in this case) -1), and sub-channel #1 is mapped to interlace # the first number to interlace # the first numberx2-1 (Miao [0079]: second sub-channel (sub-channel #1) with contiguous interlaces, mapped to interlace #3 to #5, which is from the interlace # (3 in this case) to the first numberx2-1 (3x2= 6, 6-1 = 5)).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Si to incorporate the teachings of Miao and have sub-channel #0 is mapped to interlace #0 to interlace # the first number-1, and sub-channel #1 is mapped to interlace # the first number to interlace # the first numberx2-1. Doing so would allow for sidelink communications using the properly allocated resources (Miao [0007]).
Regarding claim 37, Si modified by Miao
The method of claim 36 (the limitations of parent claim 36 as indicated above),
Si further teaches
wherein the second configuration information indicates 1 interlace per sub-channel or 2 interlaces per sub-channel (Si [0083], [0139], and [0141]: 1 or 2 interlaces per sub-channel).
Regarding claim 38, Si modified by Miao
The method of claim 37 (the limitations of parent claim 37 as indicated above),
Si further teaches
wherein based on the second configuration information indicating 1 interlace per sub-channel, an index of a first sub-channel is identical to an index of a first interlace (Si [0094]: In one example, one interlace based sub-channel can include a single interlace, e.g., L=1, and the interlace index can uniquely define the sub-channel, and e.g., the sub-channel index is the same as the interlace index.).
Regarding claim 39, Si modified by Miao
The method of claim 36 (the limitations of parent claim 36 as indicated above),
Si does not appear to explicitly teach wherein the sub-channel configuration comprises: a size of each of the sub-channel resources.
However, Miao, in the analogous art of sub-channels comprising interlaces, teaches
wherein the sub-channel configuration comprises: a size of each of the sub-channel resources (Miao [0063] and [0004]: sub-channel having a size of resources).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Si to incorporate the teachings of Miao and have the sub-channel configuration comprises: a size of each of the sub-channel resources. Doing so would allow for sidelink communications using properly allocated resources (Miao [0007]).
Regarding claim 41, Si teaches
The terminal device of claim 40 (the limitations of parent claim 40 as indicated above),
Si further teaches
wherein the first number of interlaces are contiguous interlaces (Si [0095] and [0100]: number of interlaces being contiguous interlaces),
While Si does discuss sub-channel mapping to interlaces, Si does not explicitly disclose sub-channel #0 is mapped to interlace #0 to interlace # the first number-1, and sub-channel #1 is mapped to interlace # the first number to interlace # the first numberx2-1.
However, Miao, in the analogous art of sub-channels comprising interlaces, teaches
and sub-channel #0 is mapped to interlace #0 to interlace # the first number-1 (Miao [0079]: first sub-channel (sub-channel #0) with contiguous interlaces, mapped to interlace #0 to #2 which is the first number (3 in this case) -1), and sub-channel #1 is mapped to interlace # the first number to interlace # the first numberx2-1 (Miao [0079]: second sub-channel (sub-channel #1) with contiguous interlaces, mapped to interlace #3 to #5, which is from the interlace # (3 in this case) to the first numberx2-1 (3x2= 6, 6-1 = 5)).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Si to incorporate the teachings of Miao and have sub-channel #0 is mapped to interlace #0 to interlace # the first number-1, and sub-channel #1 is mapped to interlace # the first number to interlace # the first numberx2-1. Doing so would allow for sidelink communications using the properly allocated resources (Miao [0007]).
Regarding claim 42, Si modified by Miao
The terminal device of claim 41 (the limitations of parent claim 41 as indicated above),
Si further teaches
wherein the second configuration information indicates 1 interlace per sub-channel or 2 interlaces per sub-channel (Si [0083], [0139], and [0141]: 1 or 2 interlaces per sub-channel).
Regarding claim 43, Si modified by Miao
The terminal device of claim 42 (the limitations of parent claim 42 as indicated above),
Si further teaches
wherein based on the second configuration information indicating 1 interlace per sub-channel, an index of a first sub-channel is identical to an index of a first interlace (Si [0094]: In one example, one interlace based sub-channel can include a single interlace, e.g., L=1, and the interlace index can uniquely define the sub-channel, and e.g., the sub-channel index is the same as the interlace index.).
Regarding claim 44, Si modified by Miao
The terminal device of claim 42 (the limitations of parent claim 42 as indicated above), wherein
Si does not appear to explicitly teach based on the second configuration information indicates 2 interlaces per sub-channel, each sub-channel comprises 2 contiguous interlaces, and sub-channel #0 is mapped to interlace #0 and interlace #1, sub-channel #1 is mapped to interlace #2 and interlace #3.
However, Miao, in the analogous art of sub-channels comprising interlaces, teaches
based on the second configuration information indicates 2 interlaces per sub-channel, each sub-channel comprises 2 contiguous interlaces, and sub-channel #0 is mapped to interlace #0 and interlace #1, sub-channel #1 is mapped to interlace #2 and interlace #3 (Miao [0062-0063]: 2 interlaces given as an example per sub-channel, and when using the formula derived from the example in [0079] where the interlace indices correspond to the interlace #0 to number of interlaces -1 for the sub-channel 0 and number of interlaces – (number of interlacesx2 -1) for sub-channel 1, meaning in the case where there is 2 interlaces per sub-channel, plug in 2 into the equation you get for sub-channel #0, interlace #0 – (2(number of interlaces)-1), meaning the interlaces of the first sub-channel ( #0) are interlace #0 and interlace #1, and when you plug 2 using the formula derived from [0079] for sub-channel #1, you get sub-channel #1 mapped to 2 (interlace number) through 2(interlace number)(2)-1, which gives you interlace #2 and interlace #3).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Si to incorporate the teachings of Miao and have based on the second configuration information indicates 2 interlaces per sub-channel, each sub-channel comprises 2 contiguous interlaces, and sub-channel #0 is mapped to interlace #0 and interlace #1, sub-channel #1 is mapped to interlace #2 and interlace #3. Doing so would allow for sidelink communications using the properly allocated resources (Miao [0007]).
Conclusion
The following prior art not relied upon is considered pertinent to applicant’s disclosure.
Zhao (Pub. No.: US 2024/0314812 A1) discloses M interlaces may be orthogonally multiplexed in the frequency domain, and interlace indexes thereof are 0 to M−1.
Liu (Pub. No.: US 2023/0319745 A1) discloses 0 to M-1 interlaces and C to C(K)-1 and interlaces of a resources pool.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RACHEL E MARKS whose telephone number is (703)756-1309. The examiner can normally be reached Mon-Fri 8:30am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Charles C Jiang can be reached at (571)270-7191. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.E.C./Examiner, Art Unit 2412 /CHARLES C JIANG/Supervisory Patent Examiner, Art Unit 2412
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