Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/30/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 15-19 and 26-28 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Lin (US 8705552).
Regarding claim 15, Lin discloses a method for allowing data packets in a network to arrive at the recipient at definable times, with a firewall in a computer network (reduce and bound the delay jitter of a packet in a packet switch by implementing a constant latency for each packet as it passes through a node in a packet switched network. 200 can be implemented within a network device such as a packet switch, a bridge, a router, a network interface controller (NIC), and the like; Col. 2), wherein:
each data packet is assigned a time budget for processing in the firewall, each data packet is transmitted only after the time budget has expired (egress module 222 to prevent each packet from egressing node 200 at packet egress interface 210 until occurrence of the respective eligible egress time; Col. 3), and
the time budget is defined based on the maximum possible processing time in the firewall (eligible egress time is based on the ingress time of the packet at packet ingress interface 202 and a hold interval Thold. If hold interval Thold is selected to be at least equal to, or greater than, the maximum processing time to ready any packet for transmission after being scheduled, then the output jitter is bounded to timestamp period Tper; Cols 3-4).
Regarding claim 16, Lin discloses wherein the processing time of the firewall comprises the time from the input of a data packet at the firewall via the processing to the output of the data packet at the firewall (eligible egress time module 218 to determine a respective eligible egress time at 220 for each packet based on a respective ingress time of the packet at packet ingress interface 202 and a hold interval; Col. 3).
Regarding claim 17, Lin discloses wherein the processing time additionally includes a buffer time during which the data packet is held in a buffer (eligible egress time module 218 to determine a respective eligible egress time at 220 for each packet based on a respective ingress time of the packet at packet ingress interface 202 and a hold interval; Col. 3).
Regarding claim 18, Lin discloses wherein the time budget for processing the data packet in the firewall corresponds to a definable maximum time which is greater than the maximum processing time to be expected (Each packet is processed and kept ready, but remains waiting in packet data queue 406 until its eligible egress time. The processing time for a packet can vary greatly. For example, the processing time can be very short when retrieving a packet from an on-chip memory, or can be long if requiring arbitration for transmission to an off-chip memory or device. If hold interval Thold is selected to be at least equal to, or greater than, the maximum processing time to ready any packet for transmission after being scheduled, then the output jitter is bounded to timestamp period Tper; Col. 4).
Regarding claim 19, Lin discloses wherein the data packet is transmitted to the output of the firewall after the defined maximum time has expired (Eligible egress time module 218 determines the ingress time according to the timestamp generated by timestamp module 214 upon ingress of the packet. Timestamp module 214 generates the timestamps periodically, with a programmable period Tper. The timestamp value is incremented at the start or end of each period. Hold interval Thold may be a constant, programmable, or dynamically computed value. There can be one or more Thold settings in a node. A Thold setting may apply to a single packet or set of packets, a stream or set of streams, traffic class or set of classes, or globally. In some embodiments, hold interval Thold can be selected to be greater than the time required to receive one maximum-sized packet. In some embodiments, hold interval Thold is computed according to a jitter of an immediately upstream node that is sending the packets; Cols. 3-4).
Regarding claim 26, Lin discloses wherein a time recording of the data packets takes place upon arrival at the input of the firewall (timestamp generated upon ingress of the respective packet; Col. 3).
Regarding claim 27, Lin discloses wherein the processing time corresponds to the time required by the filter processing of the firewall for one data packet (In an idle state 902, dequeue controller 604 waits for an eligible egress time to occur, that is, for the current timestamp to progress beyond ETS. When this occurs, state machine 900 moves to state 904, where dequeue controller 604 reads calendar memory 610 at address ETS (the eligible egress time for the packet). To prevent read/write contention, dequeue controller 604 reads calendar memory 610 only when enqueue state machine 800 is not in state 804. To prevent simultaneous read and write to the same memory address location, enqueue controller 602 and dequeue controller 604 access the same address ETS at different points in time. This can be guaranteed if Thold is sufficiently large. For example, in one embodiment, when Thold is zero, or is less than a minimum threshold, the calendar logic is bypassed altogether; Col. 6).
Regarding claim 28, Lin discloses wherein the buffer is arranged in the firewall (A packet ingress interface 502 ingresses packets at 504, stores the packets in a packet buffer 506, and generates a descriptor for each packet at 508. Col. 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 20-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 8705552) in view of Chan et al. (US 20230065594).
Regarding claim 20, Lin does not expressly disclose wherein a periodically repeating transmission time is defined, and the transmission of the data packet to the output of the firewall only takes place at these transmission times.
In an analogous art, Chan discloses wherein a periodically repeating transmission time is defined, and the transmission of the data packet to the output of the firewall only takes place at these transmission times (if the comparison between the latency budget and the end-to-end delay time indicates room (e.g., if the latency budget is greater than the end-to-end delay time by a sufficient amount, accounting for the uncertainty of the end-to-end delay time), packets or groups of packets can be aggregated, and periodicity of transmission can be increased. On the other hand, if the comparison between the latency budget and the end-to-end delay time indicates insufficient room, (e.g., if the end-to-end delay time is at or near the latency budget), the packets can be segmented into smaller packets and/or more clusters/groups of packets (corresponding to a shorter DRX cycle), and the periodicity of packet transmission may be decreased; [0030]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add the features taught by Chan into the system of Lin in order to determine whether delay and jitter exceed a latency budget of the packet traffic, and to schedule packets into a larger number of times slots when the latency budget is not exceeded (Chan; [0006]).
Regarding claim 21, the combination of Lin and Chan, particularly Lin discloses wherein the time budget for processing the data packet in the firewall corresponds to a definable maximum time, which is greater than the maximum processing time to be expected, along with a wait time, which is determined by the time after the processing time until the next transmission time (Each packet is processed and kept ready, but remains waiting in packet data queue 406 until its eligible egress time. The processing time for a packet can vary greatly. For example, the processing time can be very short when retrieving a packet from an on-chip memory, or can be long if requiring arbitration for transmission to an off-chip memory or device. If hold interval Thold is selected to be at least equal to, or greater than, the maximum processing time to ready any packet for transmission after being scheduled, then the output jitter is bounded to timestamp period Tper; Col. 4).
Regarding claim 22, the combination of Lin and Chan, particularly Lin discloses wherein the data packet is transmitted to the output of the firewall after the defined maximum time and the wait time have expired (Eligible egress time module 218 determines the ingress time according to the timestamp generated by timestamp module 214 upon ingress of the packet. Timestamp module 214 generates the timestamps periodically, with a programmable period Tper. The timestamp value is incremented at the start or end of each period. Hold interval Thold may be a constant, programmable, or dynamically computed value. There can be one or more Thold settings in a node. A Thold setting may apply to a single packet or set of packets, a stream or set of streams, traffic class or set of classes, or globally. In some embodiments, hold interval Thold can be selected to be greater than the time required to receive one maximum-sized packet. In some embodiments, hold interval Thold is computed according to a jitter of an immediately upstream node that is sending the packets; Cols. 3-4).
Regarding claim 23, the combination of Lin and Chan, particularly Lin discloses wherein the event that the expiration of the maximum time falls at the same point in time as a transmission time, the wait time is equal to 0 (dequeue controller 604 waits for an eligible egress time to occur, that is, for the current timestamp to progress beyond ETS. When this occurs, state machine 900 moves to state 904, where dequeue controller 604 reads calendar memory 610 at address ETS (the eligible egress time for the packet). To prevent read/write contention, dequeue controller 604 reads calendar memory 610 only when enqueue state machine 800 is not in state 804. To prevent simultaneous read and write to the same memory address location, enqueue controller 602 and dequeue controller 604 access the same address ETS at different points in time. This can be guaranteed if Thold is sufficiently large. For example, in one embodiment, when Thold is zero, or is less than a minimum threshold, the calendar logic is bypassed altogether; Col. 6).
Regarding claim 24, the combination of Lin and Chan, particularly Lin discloses wherein the time budget for processing the data packet in the firewall corresponds to the processing time, along with a wait time, which is determined by the time after the processing time until the next transmission time (Each packet is processed and kept ready, but remains waiting in packet data queue 406 until its eligible egress time. The processing time for a packet can vary greatly. For example, the processing time can be very short when retrieving a packet from an on-chip memory, or can be long if requiring arbitration for transmission to an off-chip memory or device. If hold interval Thold is selected to be at least equal to, or greater than, the maximum processing time to ready any packet for transmission after being scheduled, then the output jitter is bounded to timestamp period Tper; Col. 4).
Regarding claim 25, the combination of Lin and Chan, particularly Lin discloses wherein the data packet is transmitted to the output of the firewall after expiration of the processing time and the wait time (Eligible egress time module 218 determines the ingress time according to the timestamp generated by timestamp module 214 upon ingress of the packet. Timestamp module 214 generates the timestamps periodically, with a programmable period Tper. The timestamp value is incremented at the start or end of each period. Hold interval Thold may be a constant, programmable, or dynamically computed value. There can be one or more Thold settings in a node. A Thold setting may apply to a single packet or set of packets, a stream or set of streams, traffic class or set of classes, or globally. In some embodiments, hold interval Thold can be selected to be greater than the time required to receive one maximum-sized packet. In some embodiments, hold interval Thold is computed according to a jitter of an immediately upstream node that is sending the packets; Cols. 3-4).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Beck et al. (US 20080181112), “Methods And Apparatus For Controlling Latency Variation In A Packet Transfer Network.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OUSSAMA ROUDANI whose telephone number is (571)272-4727. The examiner can normally be reached 8:30 AM - 5:00 PM.
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/OUSSAMA ROUDANI/Primary Examiner, Art Unit 2413
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