Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This is the initial Office Action based on the application filed on
August 01, 2024. The Examiner acknowledges the following:
3. A preliminary amendment to claims was filed with claims 1 as original. Amended claims 2 – 16 and 19. Claims 17 – 18 were canceled. New claims 20 – 21 were added.
4. The specification was amended and replaced with a clean copy on the same date as to include paragraph numbers and to be in appropriate format.
5. The Abstract was amended as well.
6. The drawings filed on 08/01/2024 are accepted by the Examiner.
7. Current claims 1 – 21 are pending. Claims 17 – 18 are canceled by Applicant. Therefore, claims 1 – 16 and 19 – 21 are being considered for examination.
Information Disclosure Statement
8. The IDS documents filed on filed on 08/01/2024, 06/17/2025 and 11/26/2025 are acknowledged by the Examiner.
Priority
9. Priority data is based on a PCT application PCT/CN2023/114510, filed on 08/23/2023 and which refers to 4 (four) prior Chinese applications CN-202310729218.X; CN-202310732730.X; CN-2023-21569685.2 and CN-202321569770.9 all filed on 06/19/2023. Certified copies were mailed to the office on 08/01/2024 and were submitted again on 05/23/2026.
Claim Rejections - 35 USC § 112
10. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Regarding Claims 1 and 19:
Claim 1 discloses “a counter circuit, connected to the comparison circuit, and configured to count a first pulse signal in the first quantization time period and store a first digital code value … and store a counting result as a third digital code value …”
How the counter circuit store any digital code values, since in the specification of the current application, the counter circuit does not include any storage as to store such digital code values? As indicated in Fig 4 and paragraphs [46; 49; 50; 53; 54; 55; 57], the counter circuit 30 does not include any sort of storage for that to happen.
Furthermore, claim 1 discloses “an inversion circuit, connected to the counter circuit, and configured, in response to a triggering of …, to enable the counter circuit, in response to a triggering …, to invert the first digital code value to the second digital code value and store the second digital code value”. Nothing in the specification indicates how the counter circuit is capable of inverting the count values. How that happen?
Claim 1 also discloses “…count a first pulse signal in a first quantization time period … count a second pulse signal based on a second digital code value…” It is not clear that the second digital value is the starting value for the couniting operation during the second quantization time period.
Claim 19 recites similar limitations, which are not provided/described in the specification in a way that one with ordinary skills in the art can make any use of it.
Claims 1 and 19 are rejected under 35 U.S.C. 112(a) as for failing to comply with enablement requirement, since claim 1 includes subject matter which was not described in the specification in such a way as to enable the one skilled in the art to which it pertains, or which it is the most connected, to make and/or use of the invention.
Claims 2 – 16 and 20 – 21 are rejected under the same rationale based on its direct or indirect dependence to a rejected claim.
Claim Rejection under 35 U.S.C. 112(b)
11. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Regarding Claim 1:
Claims 1 recites “a counter circuit, connected to the comparison circuit, and configured to count a first pulse signal in the first quantization time period and store a first digital code value … and store a counting result as a third digital code value …”
How the counter circuit stores any digital code values, since the counter circuit does not include any storage as to store such digital code values? Where are these values stored? The claim language is confusing and misleading and it is not clear what the inventor(s) is/are pursuing as their invention.
Furthermore, claim 1 discloses “an inversion circuit, connected to the counter circuit, and configured, in response to a triggering of …, to enable the counter circuit, in response to a triggering …, to invert the first digital code value to the second digital code value and store the second digital code value”. Nothing in the claim as written indicates the counter circuit is capable of inverting the count values. How that happen?
Claim 1 also discloses “…count a first pulse signal in a first quantization time period … count a second pulse signal based on a second digital code value…” It is not clear that the second digital value is the starting value for the couniting operation during the second quantization time period.
Claim 19 presents similar issues as claim 1 and it is rejected under a similar rationale.
Claims 1 and 19 are rejected under 35 U.S.C. 112(b) because the claim language is confusing and misleading and it is not clear what the inventor(s) is/are pursuing as their invention.
Claims 2 – 16 and 20 – 21 are rejected under the same rationale based on its direct or indirect dependence to a rejected claim.
Claim Rejections - 35 USC § 102
12. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 5 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Kyung-min Kim et al., US 2015/0129748 A1, hereinafter Kim”. (Note: Kim is art is from the IDS document).
Note: the rejection under 35 U.C. 112(a) and 35 U.S.C. 112(b) has been taken into account for the rejections written below.
Regarding Claims 1 and 19:
Kim teaches
An image sensor comprising: a pixel array having an plurality of pixels, each pixel generating a respective pixel signal; an analog-to-digital converter for converting the respective pixel signal into a digital signal; and an image signal processor for processing the digital signal, wherein the analog-to-digital converter includes: a reference generator for generating a reference signal indicating a start time point; a comparator for comparing the reference signal with the pixel signal to generate a termination signal indicating a termination time point; and a counter for counting from the start time point to the termination time point to generate the digital signal, the counter including: a first clock buffer configured to buffer a first clock signal to generate a first buffered clock signal; a second clock buffer configured to buffer a second clock signal to generate a second buffered clock signal, wherein the first clock signal is phase-shifted from the second clock signal, and the first and second buffered clock signals are gray code bits corresponding to two less significant bit signals of the digital signal; and a ripple counter configured to generate at least one more significant bit signal of the digital signal by sequentially toggling in response to one of the first and second buffered clock signals, wherein the first and second buffered clock signals are phase-shifted by 90.degree. with the digital signal being updated four-times every period of the clock signal to form a quadruple data rate (QDR) counter, further comprising: an analog correlated double sampling (CDS) unit that generates the pixel signal that is a difference between a respective reset signal and a respective measured image signal generated by the pixel; and a latch that stores the digital signal output by the counter at the termination time point and, further comprising: a first latch that stores a first digital signal output by the counter at a first termination time point generated when the pixel signal is a reset signal; and a second latch that stores a second digital signal output by the counter at a second termination time point generated when the pixel signal is a measured image signal, wherein the image signal processor determines a difference between the first and second digital signals for digital correlated double sampling and, wherein the counter is configured to count from a first start time point to a first termination time point to generate a first digital signal that is inverted after the first termination time point to generate a negative digital signal, and wherein the counter is configured to count during a second start time point to a second termination time point starting from the inverted digital signal to generate a second digital signal, and wherein the first termination time point corresponds to the pixel signal being a reset signal and the second termination time point corresponds to the pixel signal being a measured image signal.
As for claims 1 and 2, Kim teaches,
Regarding Claim 1:
A readout circuit of an image sensor (Fig 22, image sensor 600 includes a plurality of MDR counters, pixel array 610. See [0215]), comprising:
a ramp voltage circuit (Kim, Fig 22, reference signal generator or ramp circuit 640. See [0215]), configured to output a ramp voltage signal in a first quantization time period and a second quantization time period of a pixel unit respectively (Figs. 28A and 28B are timing diagrams of signals during the counting operation with the inversion function in the counter 100k of Fig 24. Referring to Figs. 28A and 28B, the counter 100k having the inversion function first performs a first counting operation for converting the analog reset signal into a first count that digitally represents the reset signal. Thereafter, an inversion operation is performed for inverting the first count. Additionally, a second counting operation is performed for counting with the analog measured image signal from the inversion of the first count to generate a second count that represents the final image signal that is a difference of the reset signal and the measured image signal. For example, the first and second counting are up-counting operations as illustrated in Figs 28A and 28B. the reset signal is 2 in the first count and the corresponding measured signal is 4 on the second count. See [0236; 0237; 0241 – 0248]);
a comparison circuit (Fig 22, comparison circuit 660. See [0215]), having a first input end connected to the pixel unit and a second input end connected to the ramp voltage circuit (Fig 22, comparison circuit 660 is connected to ramp circuit 640, to MDR counter 700 and to the pixel array 610. See [0215 – 0218]), and configured to compare a reset signal or a pixel signal output from the pixel unit with the ramp voltage signal and output a reset pulse signal or a pixel pulse signal (See [0256; 0256]);
a counter circuit (Fig 22, multiple data rate (MDR) counter MDR 700. See [0217]), connected to the comparison circuit, and configured to count a first pulse signal in the first quantization time period and store a first digital code value (First count, as seen in Fig 28A. Fig 29, at time t11, the pixel voltage signal Vpix is at the level representing the reset signal. At t12, the voltage levels of the ramp signal RAMP and the pixel voltage signal Vpix become equal to each other such that the comparison signal CMP of the comparator 661 transitions to logic low from logic high for indicating a first termination time point Te of the first counting operation. In response to the falling edge of the comparison signal CMP, the first count (Vrst=3) corresponding to the reset signal is stored in the counter 100k. See [0252]); and count a second pulse signal based on a second digital code value in the second quantization time period and store a counting result as a third digital code value (Fig 28A, 28B, second count. Fig 29, At time t16, the voltage levels of the ramp signal RAMP and the pixel voltage signal Vpix become equal to each other such that the comparison signal CMP of the comparator 661 transitions to logic low for indicating a second termination time point of the second counting operation. In response to the falling edge of the comparison signal CMP, the difference (Vsig-1=3) between the first and second count is generated by the counter 700 for representing the final image signal that is the difference between the rest signal (Vrst=3) and the measured image signal (Vrst+Vsig=7). See [0256]), wherein the first pulse signal and the second pulse signal are respectively the reset pulse signal and the pixel pulse signal, or the first pulse signal and the second pulse signal are respectively the pixel pulse signal and the reset pulse signal (Fig 29, At time t16, the voltage levels of the ramp signal RAMP and the pixel voltage signal Vpix become equal to each other such that the comparison signal CMP of the comparator 661 transitions to logic low for indicating a second termination time point of the second counting operation. In response to the falling edge of the comparison signal CMP, the difference (Vsig-1=3) between the first and second count is generated by the counter 700 for representing the final image signal that is the difference between the rest signal (Vrst=3) and the measured image signal (Vrst+Vsig=7). See [0256]); and
an inversion control circuit (Fig 22, control circuit630, wherein the control signals CTRL may include signals INV1 and INV2 for controlling the inversion operation of the counting block 680. See [0216]), connected to the counter circuit, and configured, in response to a triggering of a mode selection signal (Fig 25, inversion control signal INV1. See [0230; 0231]), to output an inversion control signal (Fig 25, inversion control signal INV2. See [0230; 0231) between the first quantization time period and the second quantization time period, to enable the counter circuit, in response to a triggering of the inversion control signal, to invert the first digital code value to the second digital code value and store the second digital code value (A second counting operation is performed for counting with the analog measured image signal from the inversion of the first count to generate a second count that represents the final image signal that is a difference of the reset signal and the measured image signal. For example, the first and second counting are up-counting operations as illustrated in Figs 28A and 28B See [0237]).
Regarding Claim 2:
The rejection of claim 1 is incorporated herein. As for wherein the counter circuit is configured to count the reset pulse signal in the first quantization time period and store the first digital code value, and count the pixel pulse signal based on the second digital code value in the second quantization time period and store the counting result as the third digital code value (Fig 28A and 28 B shows a digital double sampling DDS show the reset signal being 2 and the measured signal being 4, wherein the reset pulse signal is count in the 1st COUNT and the second digital code value in the 2nd COUNT. See [0242 – 0248]); or alternatively, the counter circuit is configured to count the pixel pulse signal in the first quantization time period and store the first digital code value, and count the reset pulse signal based on the second digital code value in the second quantization time period and store the counting result as the third digital code value (Nothing in Kim Figs 28A and 28 B precludes that the pixel signal pulse signal during the 1st COUNT and the reset pulse signal to happen during the 2nd COUNT. See [0242 – 0248]).
Regarding Claims 3 and 4:
The rejection of claim 1 is incorporated herein. As for claim 3, Kim Fig 24 shows the counter circuit 100k with a first counting unit 110A, a second counting unit 120k, a third counting unit 130k and a fourth counting unit 140k, an inversion control circuit which outputs the selected inversion signals INV1 and INV2, wherein the first counting unit 110k is implemented with a first latch having a data terminal D receiving an input clock signal CLK1, a clock terminal CK receiving a comparison signal CMP indicating the termination time point Te of the counting operation and an output terminal Q outputting a first bit signal D[0]. The ripple counter 30k including the subsequent counting units 120k, 130k and 140k generates the most significant bit signals D[1], D[2] and D[3] which are sequentially toggling. Fig 25, the second counting unit 120k includes a flip-flop 731 and an inversion multiplexer 732. The inversion multiplexer 732 selects one of an output of the previous counting unit (which is, the latch output signal Lout) and a second inversion control signal INX2 in response to a first inversion control INV1 to generate an output signal OUT2 to the next counting unit (i.e., the third counting unit 130k). See [0227 – 0232].
As for the additional limitations of Claim 4: Fig 26 includes an AND gate 60, which is also included in the control circuit 630 of Fig 22 for generating a clock signal CLKC that is activated to toggle as another clock signal CLK when the count enables signal CNT-EN is activated to logic high. See [0235].
Regarding Claim 5:
The rejection of claims 1 and 3 is incorporated herein. As for the additional limitations of claim 5: Fig 20, plurality of storage latches 471 (See [0201]); Fig 21, first latch 571 and respective second latch 573 (See [0209]).
Regarding Claim 19:
The rejection of claim 1 is incorporated herein. As for claim 19, Kim teaches,
An image sensor (Fig 22, image sensor 600. See [0215]), comprising; a pixel array (Fig 22, pixel array 610 includes a plurality of pixels. See [0215]), comprising a plurality of pixel units arranged in an array; a control circuit (Fig 22, control circuit 630. See [0215]); and
a plurality of readout circuits (Fig 22 shows a readout circuit 600. See [0215 – 0218]), respectively connected to the control circuit, wherein each of the plurality of readout circuits is further connected to a plurality of pixel units arranged in a column (Fig 22 shows a readout circuit 600 with the pixel array 610, a reference circuit 640, a comparison circuit 660, a control unit 630 and a MDR counter 700. Pixels in the array 610 are understood as arranged in rows and columns. See [0215 – 0218]), and comprises:
a ramp voltage circuit Kim, Fig 22, reference signal generator or ramp circuit 640. See [0215]), configured to output a ramp voltage signal in a first quantization time period and a second quantization time period of connected pixel units respectively (Figs. 28A and 28B are timing diagrams of signals during the counting operation with the inversion function in the counter 100k of Fig 24. Referring to Figs. 28A and 28B, the counter 100k having the inversion function first performs a first counting operation for converting the analog reset signal into a first count that digitally represents the reset signal. Thereafter, an inversion operation is performed for inverting the first count. Additionally, a second counting operation is performed for counting with the analog measured image signal from the inversion of the first count to generate a second count that represents the final image signal that is a difference of the reset signal and the measured image signal. For example, the first and second counting are up-counting operations as illustrated in Figs 28A and 28B. the reset signal is 2 in the first count and the corresponding measured signal is 4 on the second count. See [0236; 0237; 0241 – 0248]);
a comparison circuit (Fig 22, comparison circuit 660. See [0215]), having a first input end connected to the connected pixel units and a second input end connected to the ramp voltage circuit (Fig 22, comparison circuit 660 is connected to ramp circuit 640, to MDR counter 700 and to the pixel array 610. See [0215 – 0218]), and configured to compare a reset signal or a pixel signal output from the connected pixel units with the ramp voltage signal and output a reset pulse signal or a pixel pulse signal (See [0256; 0256]);
a counter circuit (Fig 22, multiple data rate (MDR) counter MDR 700. See [0217]), connected to the comparison circuit, and configured to count a first pulse signal in the first quantization time period and store a first digital code value (First count, as seen in Fig 28A. Fig 29, at time t11, the pixel voltage signal Vpix is at the level representing the reset signal. At t12, the voltage levels of the ramp signal RAMP and the pixel voltage signal Vpix become equal to each other such that the comparison signal CMP of the comparator 661 transitions to logic low from logic high for indicating a first termination time point Te of the first counting operation. In response to the falling edge of the comparison signal CMP, the first count (Vrst=3) corresponding to the reset signal is stored in the counter 100k. See [0252]); and count a second pulse signal based on a second digital code value in the second quantization time period and store a counting result as a third digital code value (Fig 28A, 28B, second count. Fig 29, At time t16, the voltage levels of the ramp signal RAMP and the pixel voltage signal Vpix become equal to each other such that the comparison signal CMP of the comparator 661 transitions to logic low for indicating a second termination time point of the second counting operation. In response to the falling edge of the comparison signal CMP, the difference (Vsig-1=3) between the first and second count is generated by the counter 700 for representing the final image signal that is the difference between the rest signal (Vrst=3) and the measured image signal (Vrst+Vsig=7). See [0256]), wherein the first pulse signal and the second pulse signal are respectively the reset pulse signal and the pixel pulse signal, or the first pulse signal and the second pulse signal are respectively the pixel pulse signal and the reset pulse signal (Fig 29, At time t16, the voltage levels of the ramp signal RAMP and the pixel voltage signal Vpix become equal to each other such that the comparison signal CMP of the comparator 661 transitions to logic low for indicating a second termination time point of the second counting operation. In response to the falling edge of the comparison signal CMP, the difference (Vsig-1=3) between the first and second count is generated by the counter 700 for representing the final image signal that is the difference between the rest signal (Vrst=3) and the measured image signal (Vrst+Vsig=7). See [0256]); and
an inversion control circuit (Fig 22, control circuit630, wherein the control signals CTRL may include signals INV1 and INV2 for controlling the inversion operation of the counting block 680. See [0216]), connected to the counter circuit, and configured, in response to a triggering of a mode selection signal (Fig 25, inversion control signal INV1. See [0230; 0231]), to output an inversion control signal between the first quantization time period and the second quantization time period, to enable the counter circuit, in response to a triggering of the inversion control signal, to invert the first digital code value to the second digital code value and store the second digital code value (A second counting operation is performed for counting with the analog measured image signal from the inversion of the first count to generate a second count that represents the final image signal that is a difference of the reset signal and the measured image signal. For example, the first and second counting are up-counting operations as illustrated in Figs 28A and 28B See [0237]).
Conclusion
13. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
1. T. Cho, US 11,689,831 B2 – it teaches an image sensor, comprising: a pixel outputting a pixel signal; a ramp voltage generation circuit suitable for generating a ramp voltage that changes at a first slope in a first section and generating the ramp voltage that changes at a second slope having a greater absolute value than the first slope in a second section following the first section; an operation amplifier suitable for comparing the pixel signal with the ramp voltages during the first section and the second section; and a counter circuit suitable for generating a digital code corresponding to the pixel signal in response to an output of the operation amplifier, wherein the counter circuit generates the digital code by counting a clock until the output of the operation amplifier transitions in the first section, and wherein when the output of the operation amplifier does not transition in the first section, the counter circuit generates the digital code by counting the clock until the output of the operation amplifier transitions in the second section.
2. J. Jun et al., US 2023/0155602 A1 – it teaches a circuit, comprising: a first amplifier configured to operate based on a first power supply voltage and to generate a first output signal by comparing a ramp signal and a reset signal of a pixel signal output from a pixel array during a first operation period and comparing the ramp signal and an image signal of the pixel signal output from the pixel array during a second operation period; a second amplifier configured to operate based on the first power supply voltage and to generate a second output signal based on the first output signal; and a counter configured to operate based on a second power supply voltage, to count pulses of the second output signal, and to output a counting result as a digital signal, wherein a first level of the first power supply voltage is greater than a second level of the second power supply voltage, and wherein the second amplifier is further configured to adjust a voltage level of the second output signal from a low level to a third level, wherein the third level is less than or equal to the second level of the second power supply voltage, wherein the second amplifier includes: a first transistor configured to provide the first power supply voltage to a first output node, from which the second output signal is output, in response to the first output signal; a clipping circuit coupled between a power supply voltage terminal and the first transistor, and configured to adjust the voltage level of the second output signal by causing a voltage drop between the power supply voltage terminal and the first transistor; and a current source coupled with the first transistor through the first output node, and configured to generate a power current.
3. J. Jun et al., US 12,563,318 B2 – it teaches an image sensor comprising: a pixel array configured to output a first pixel signal corresponding to a first conversion gain from a first pixel and output a second pixel signal corresponding to a second conversion gain from the first pixel; and an analog-to-digital converting circuit configured to output a first digital signal corresponding to the first pixel signal, wherein the analog-to-digital converting circuit is configured to output a second digital signal corresponding to the second pixel signal based on a value of the first digital signal, wherein the first conversion gain is higher than the second conversion gain, and wherein the analog-to-digital converting circuit is configured to output the second digital signal based on a comparison result between a value of at least a portion of bits of the first digital signal and a threshold value, wherein the pixel array comprises a floating diffusion region connected to the first pixel and a plurality of pixels connected to the floating diffusion region, wherein the floating diffusion region has a first capacitance value when the pixel array outputs the first pixel signal, and wherein the floating diffusion region has a second capacitance value greater than the first capacitance value when the pixel array outputs the second pixel signal, wherein the analog-to-digital converting circuit is configured to output the second digital signal when the value of at least a portion of bits of the first digital signal is greater than the threshold value and, wherein the analog-to-digital converting circuit is configured not to generate the second digital signal when the value of at least a portion of bits of the first digital signal is smaller than or equal to the threshold value.
Contact
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARLY S. B. CAMARGO whose telephone number is (571)270-3729. The examiner can normally be reached on M-F 8:00 - 5:99 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached on (571)272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MARLY S CAMARGO/ Primary Examiner, Art Unit 2638
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