DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/02/2025 and 12/19/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 2-18 are objected to because of the following informalities:
Claims 2-18- “An apparatus” in line 1 should be “The apparatus”
Claim 7 line 2- “the single capability vector indication field” should be “the single capability indication field” to be consistent with how this term is introduced in claim 6
Claim 13 line 5- insert --the-- before “memory” to clarify that this refers to the same memory introduced in claim 1
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because it is directed to a computer program per se without any structural recitations.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a given vector memory access instruction specifying a plurality of memory access operations, where each memory access operation is to be performed to access an associated data element” in lines 7-8 and “to enable performance of the memory access operation for each data element for which the memory access operation is allowed” in lines 25-26. It is unclear how each memory access operation of the given vector memory access instruction is to be performed when performance is only enabled for memory access operations that are allowed. For purposes of examination, the claim will be interpreted as only requiring performance of memory access operations that are allowed.
Claims 19-20 are rejected for the same reasons as they recite the same limitation and the same interpretation will be taken for purposes of examination.
Claim 1 recites “the vector processing operations specified by the vector instructions” in line 5. It is unclear whether this refers to the vector processing operations introduced in line 2 or other vector processing operations. For purposes of examination, the vector instructions will be interpreted as specifying the vector processing operations introduced in line 2.
Claims 19-20 are rejected for the same reasons as they recite the same limitation and the same interpretation will be taken for purposes of examination.
Claim 1 recites “each given data element in the plurality of data elements” in line 20. There is insufficient antecedent basis for this limitation as the claim does not introduce the plurality of data elements as having given data elements. For purposes of examination, the plurality of data elements will be interpreted as having given data elements. Examiner suggests clarifying that each respective capability is associated with a given data element in the plurality of data elements in lines 13-14.
Claims 19-20 are rejected for the same reasons as they recite the same limitation and the same interpretation will be taken for purposes of examination.
Claim 1 recites “the associated capability” in line 21 and line 24. It is unclear which capability this refers to as line 13 introduces a plurality of capabilities. For purposes of examination, this will be interpreted as referring to a capability associated with one of the data elements.
Claims 19-20 are rejected for the same reasons as they recite the same limitation and the same interpretation will be taken for purposes of examination.
Claim 1 recites “the memory access operation to be used to access the given data element” in line 22. There is insufficient antecedent basis for this limitation as the claim does not introduce a memory access operation that is used to access the given data element. For purposes of examination, this limitation will be interpreted as one of the plurality of memory access operations that is used to access the given data element.
Claims 19-20 are rejected for the same reasons as they recite the same limitation and the same interpretation will be taken for purposes of examination.
Claim 1 recites “the memory access operation” in line 25. It is unclear which of the plurality of memory access operations introduced in line 8 this refers to or if it refers to the memory access operation described in line 22. For purposes of examination, this will be interpreted as the memory access operation described in line 22.
Claims 19-20 are rejected for the same reasons as they recite the same limitation and the same interpretation will be taken for purposes of examination.
Claim 1 recites “the memory access operation for any given data element” in lines 26-27. There is insufficient antecedent basis for this limitation as the claim does not introduce any given data element as having a memory access operation. For purposes of examination, this will be interpreted as any memory access operation for any given data element.
Claims 19-20 are rejected for the same reasons as they recite the same limitation and the same interpretation will be taken for purposes of examination.
Claim 1 recites “the determined memory address” in lines 27-28. It is unclear which determined memory address introduced in lines 20-21 this refers to. For purposes of examination, this will be interpreted as the determined memory address for any one of the given data elements.
Claims 19-20 are rejected for the same reasons as they recite the same limitation and the same interpretation will be taken for purposes of examination.
Claim 2 recites “each capability sized block within given vector registers of the set of vector registers” in lines 2-3. There is insufficient antecedent basis for this limitation as the claim does not introduce capability sized bocks or given vector registers of the set of vector registers. For purposes of examination, the set of vector registers will be interpreted as having given registers with capability sized blocks.
Claim 2 recites “the associated capability sized block” in lines 4-5. There is insufficient antecedent basis for this limitation as the claim does not introduce an associated capability sized block. For purposes of examination, this limitation will be interpreted as any capability sized block.
Claim 4 recites “the associated capability sized block” in line 3. There is insufficient antecedent basis for this limitation as the claim does not introduce an associated capability sized block. For purposes of examination, this limitation will be interpreted as any capability sized block.
Claim 8 recites “the associated capabilities” in line 3. It is unclear which capabilities this refers to as the claim does not describe capabilities associated with a given pair of data elements. For purposes of examination, this limitation will be interpreted as any capabilities associated with a given pair of data elements.
Claim 9 recites “each data element” in line 3. It is unclear which data element this refers to as claim 1 introduces “an associated data element” in line 9, “a plurality of data elements” in line 11, given data elements in line 20, and data elements for which the memory access operation is allowed in lines 25-26. For purposes of examination, this limitation will be interpreted as referring to each of the plurality of data elements.
Claim 9 recites “a given data element” in line 7. It is unclear if this given data element is the same as the given data element introduced in claim 1 line 20, claim 1 line 27, or if it is different. For purposes of examination, this limitation will be interpreted as referring to a different given data element.
Claim 9 recites “the vector register containing the associated capability” in line 7. It is unclear which vector register and associated capability this refers to as claim 1 introduces a plurality of vector registers containing a plurality of capabilities. For purposes of examination, this limitation will be interpreted as any vector register containing a capability.
Claim 9 recites “the associated capability” in line 9. It is unclear which capability this refers to as claim 1 introduces a plurality of capabilities. For purposes of examination, this limitation will be interpreted as a capability associated with one of the data elements.
Claim 9 recites “the corresponding data lane” in lines 10-11. It is unclear which corresponding data lane this refers to as claim 9 introduces a corresponding lane associated with each data element and it is unclear if the given data element introduced in line 7 is one of the data elements associated with a corresponding data lane. For purposes of examination, this limitation will be interpreted as a data lane corresponding to the given data element introduced in line 7.
Claim 10 recites “the data lane associated with the given data element” in line 5. It is unclear whether the given data element in this limitation refers to the given data element introduced in claim 9 or one of the given data elements introduced in claim 1. Further, there is insufficient antecedent basis for this limitation as the claim does not introduce a data lane that is associated with any given data element.
Claim 10 recites “the associated capability” in line 6 and lines 8-9. It is unclear which capability this refers to as claim 1 introduces a plurality of capabilities. For purposes of examination, this limitation will be interpreted as a capability associated with one of the data elements.
Claim 11 recites “each data element” in line 6. It is unclear which data element this refers to as claim 1 introduces “an associated data element” in line 9, “a plurality of data elements” in line 11, given data elements in line 20, and data elements for which the memory access operation is allowed in lines 25-26. For purposes of examination, this limitation will be interpreted as referring to each of the plurality of data elements.
Claim 11 recites “the associated capability” in line 6. It is unclear which capability this refers to as claim 1 introduces a plurality of capabilities. For purposes of examination, this limitation will be interpreted as a capability associated with one of the data elements.
Claim 12 recites “the memory access operations for the data elements” in line 2. It is unclear if this refers to each memory access operations performed to access an associated data element as described in claim 1 lines 8-9 or if it refers to memory access operations for the other data elements introduced in claim 1. For purposes of examination, the former interpretation will be taken.
Claim 13 recites “a plurality of capabilities” in line 4. It is unclear whether this is the same as the plurality of capabilities introduced in claim 1 or if they are different. For purposes of examination, they will be interpreted to be different.
Claim 13 recites “the plurality of capabilities” in lines 5-7 and “said plurality” in line 7. It is unclear whether this refers to the plurality of capabilities introduced in line 4 or claim 1. For purposes of examination, this will be interpreted as referring to the plurality of capabilities introduced in line 4.
Claim 13 recites “the rearrangement specified by the access pattern” in line 5. There is insufficient antecedent basis for this limitation as the claim does not introduce a rearrangement that is specified by the access pattern- although claim 13 describes a rearrangement, claim 13 does not describe that the rearrangement is specified by the access pattern. For purposes of examination, this rearrangement and the rearrangement in claim 13 will be interpreted as being specified by the access pattern.
Claim 16 recites “the data elements” in line 4. It is unclear which data elements this refers to as claim 1 introduces “an associated data element” in line 9, “a plurality of data elements” in line 11, given data elements in line 20, and data elements for which the memory access operation is allowed in lines 25-26. For purposes of examination, this limitation will be interpreted as referring to the plurality of data elements.
Claim 17 recites “each given data element in the plurality of data elements” in lines 3-4. There is insufficient antecedent basis for this limitation as the claim does not describe the plurality of data elements having given data elements. For purposes of examination, the plurality of data elements will be interpreted as having given data elements which this limitation refers to.
Claim 17 recites “the given data element” in line 4. It is unclear if this given data element is the same as the given data element introduced in claim 1 line 20, claim 1 line 27, or line 3. For purposes of examination, this limitation will be interpreted as referring to each of the given data elements introduced in claim 1 line 20.
Claim 17 recites “the associated capability” in line 4. It is unclear which capability this refers to as claim 1 introduces a plurality of capabilities. For purposes of examination, this limitation will be interpreted as a capability associated with one of the data elements.
Claim 18 recites “each given data element” in lines 3-4. It is unclear whether this refers to the same given data elements introduced in claim 1 line 20, claim 1 line 27, or if they are different. For purposes of examination, this will be interpreted as the same as claim 1 line 20.
Claim 18 recites “the associated capability” in line 4. It is unclear which capability this refers to as claim 1 introduces a plurality of capabilities. For purposes of examination, this limitation will be interpreted as a capability associated with one of the data elements.
Claims dependent on a rejected base claim are further rejected based on their dependence.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 19 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Meadows US 2019/0205137.
19. A method of performing memory access operations within an apparatus providing processing circuitry to perform vector processing operations and a set of vector registers (Fig. 12 and [0123]-[0125] discloses performing a multi-load vector instruction (i.e., memory access operations) within a processor/apparatus providing a core/processing circuitry to perform vector processing operations (i.e., the operations corresponding to the multi-load vector instruction are vector processing operations) and a set of vector registers 1206), the method comprising:
employing an instruction decoder, in response to a given vector memory access instruction specifying a plurality of memory access operations, where each memory access operation is to be performed to access an associated data element, to determine, from a data vector indication field of the given vector memory access instruction, at least one vector register in the set of vector registers associated with a plurality of data elements, and to determine, from at least one capability vector indication field of the given vector memory access instruction, a plurality of vector registers in the set of vector registers containing a plurality of capabilities, each capability being associated with one of the data elements in the plurality of data elements and providing an address indication and constraining information constraining use of that address indication when accessing memory, wherein the number of vector registers determined from the at least one capability vector indication field is greater than the number of vector registers determined from the data vector indication field (since this limitation is contingent on there being a given memory access instruction, it is a contingent limitation that is not required under BRI of a method claim, see MPEP 2111.04 (II));
controlling the processing circuitry:
to determine, for each given data element in the plurality of data elements, a memory address based on the address indication provided by the associated capability, and to determine whether the memory access operation to be used to access the given data element is allowed in respect of that determined memory address having regard to the constraining information of the associated capability (this limitation is not required since it recites elements (i.e., the plurality of data elements, the address indication, the memory access operation, etc.) that follow from the contingent limitation and are not required); and
to enable performance of the memory access operation for each data element for which the memory access operation is allowed, where performance of the memory access operation for any given data element causes that given data element to be moved between the determined memory address in the memory and the at least one vector register (this limitation is not required since it recites elements (i.e., the memory access operation, the memory, the at least one vector register) that follow from a contingent limitation and are not required).
Prior Art Considerations
While no prior art rejection is given for claims 1 and 20, these claims are currently rejected under 112(b)/101 and are not allowable at the current point. The following is a statement of the prior art considerations given for these claims:
The known prior art of record, taken alone or in combination, was not found to teach, in combination with other limitations in the claim, a vector memory access instruction having a data vector indication field used to determine at least one vector register associated with a plurality of data elements and a capability vector indication field used to determine a plurality of vector registers containing a plurality of capabilities, each capability being associated with one of the plurality of data elements and providing an address indication and constraining information constraining use of that address indication when accessing memory, where the number of vector registers determined from the capability vector indication field is greater than the number of vector registers determined from the data vector indication field, as required in claims 1 and 20.
The closest prior art of record was found to be:
Meadows US 2019/0205137- which teaches multi-load and multi-store vector instructions, see Abstract.
Waterman US 2023/0305969- which teaches a memory protection circuit that checks whether accessing elements of a subvector will cause a memory protection violation by inputting the address of the first and last element, see [0051] and Fig. 4.
LeMay US 2023/0195461 which teaches an instruction comprising fields to indicate a memory address that stores a capability and a single destination register, the capability comprising an address field, validity field, and bounds field, where the capability may be split between multiple general-purpose registers and/or capability registers, see Abstract and [0068].
Barnes US 2018/0349294 teaches performing a range check operation to determine whether access to a memory address is permitted responsive to execution of a memory access instruction identifying a pointer that identifies the memory address, see Abstract.
LeMay US 2021/0200546 teaches checking permissions for a memory access based on a pointer in the memory operand, see Fig. 2
While the known prior art of record was found to generally teach vector memory access instructions (Meadows, Waterman) and memory access instructions using capabilities (LeMay, Barnes) the known prior art of record was not found to teach the specific features of the vector memory access instruction required by claims 1 and 20.
Conclusion
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/KASIM ALLI/Examiner, Art Unit 2183 /JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183