DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 5-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation " the semiconductor layer of the first semiconductor substrate" in line 4. There is insufficient antecedent basis for this limitation in the claim and it is unclear what component is considered to be the semiconductor layer of the first semiconductor substrate as claimed.
Claim 5 recites the limitation “wherein the lower electrode has a shape in which an upper surface of the lower electrode is higher than a height of a surface of the second semiconductor substrate on the interlayer film side” in lines 3-5. This limitation contradicts the limitation of claim 1 which explicitly states “the through electrode includes a lower electrode provided from substantially the same height as a surface of the second semiconductor substrate on the interlayer film side toward the second semiconductor substrate” in lines 13-15. It is unclear how the surface of the lower electrode layer can be substantially the same and also lower than the surface of the second semiconductor substrate on the interlayer film side.
Claim 6 recites the limitation “wherein the lower electrode has a shape in which an upper surface of the lower electrode is lower than a height of a surface of the second semiconductor substrate on the interlayer film side” in lines 3-6. This limitation contradicts the limitation of claim 1 which explicitly states “the through electrode includes a lower electrode provided from substantially the same height as a surface of the second semiconductor substrate on the interlayer film side toward the second semiconductor substrate” in lines 13-15. It is unclear how the surface of the lower electrode layer can be substantially the same and also lower than the surface of the second semiconductor substrate on the interlayer film side.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7, and 9-10 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Saka et al. (WO 2020262559 A1; hereinafter “Saka”), US 2022/0367540 A1 is used as a translation for WO 2020262559 A1.
In regard to claim 1, Saka teaches a solid-state imaging element (an imaging device) (Fig. 1 and paragraph116), comprising:
a first semiconductor substrate (a first substrate 100) provided with a photodiode (photodiode PD) and some pixel transistors (transfer transistor TR) for each pixel (the first substrate 100 is provided with the plurality of pixels 541A, 541B, 541C, and 541D, and each of these pixels 541 includes a photodiode PD) (Fig. 6 and paragraphs 132 and 140);
a second semiconductor substrate (a semiconductor layer 200S of a second substrate 200) bonded to the first semiconductor substrate and provided with another pixel transistor (pixel circuit 210) other than the some pixel transistors constituting the pixel (the first substrate 100, the second substrate 200, and the third substrate 300 are bonded together and the pixel circuit 210 provided to the semiconductor layer 200S and is alternatively referred to as pixel transistor circuit) (Fig. 6, paragraphs 131-132 and 176);
an interlayer film (interlayer insulating films 222) stacked on a surface (top surface) of the second semiconductor substrate via an insulating film (the interlayer insulating film 222 is shown on the semiconductor layer 200S via a passivation film 221 in Fig. 6) (Fig. 6 and paragraph 214), the surface being opposite to a surface on a side to which the first semiconductor substrate is bonded (the interlayer insulating films 222 is shown on the top surface of the semiconductor layer 200S and the first substrate 100 is shown on the bottom surface of semiconductor layer 200S in Fig. 6); and
a through electrode (a through electrode TGV) that penetrates the second semiconductor substrate from the interlayer film side and is electrically connected to the first semiconductor substrate (the through electrode TGV is shown penetrating from the interlayer insulating films 222 to the first substrate 100 in Fig. 6) (Fig. 6, Fig. 14A and paragraph 153),
wherein the through electrode includes a lower electrode provided from substantially the same height as a surface of the second semiconductor substrate on the interlayer film side toward the second semiconductor substrate (a portion of the through electrode TGV starting at the surface of the semiconductor layer 200S functions as the lower electrode and is shown at in annotated Fig. 14A below), and an upper electrode penetrating the interlayer film and connected to the lower electrode (a portion of the through electrode TGV starting above the surface of the semiconductor layer 200S functions as the upper electrode and is shown connected to the lower portion in annotated Fig. 14A below).
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In regard to claim 7, Saka teaches wherein in a case where the first semiconductor substrate and the second semiconductor substrate are at the same potential, the upper electrode constituting the through electrode is configured in a shape connected also to the second semiconductor substrate, the through electrode supplying a potential to the first semiconductor substrate and the second semiconductor substrate (as the through electrode TGV is electrically connected to the first substrate 100 and the second substrate 200, the through electrode provides potential to the first semiconductor substrate and the second semiconductor substrate) (Fig. 6 and paragraph 140).
In regard to claim 9, Saka teaches a method of manufacturing, a solid-state imaging element (an imaging device) (Fig. 1 and paragraph116), the method comprising:
bonding a second semiconductor substrate (a semiconductor layer 200S of a second substrate 200) to a first semiconductor substrate (a first substrate 100) provided with a photodiode (photodiode PD) and some pixel transistors (transfer transistor TR) for each pixel (the first substrate 100 is provided with the plurality of pixels 541A, 541B, 541C, and 541D, and each of these pixels 541 includes a photodiode PD and is bonded to the second substrate 200) (Fig. 6 and paragraphs 131-132, 140 and 176);
the second semiconductor substrate (a semiconductor layer 200S of a second substrate 200) being provided with another pixel transistor (pixel circuit 210) other than the some pixel transistors constituting the pixel (the pixel circuit 210 provided to the semiconductor layer 200S and is alternatively referred to as pixel transistor circuit) (Fig. 6, paragraphs 132);
stacking an interlayer film (interlayer insulating films 222) on a surface (top surface) of the second semiconductor substrate via an insulating film (the interlayer insulating film 222 is shown on the semiconductor layer 200S via a passivation film 221 in Fig. 6) (Fig. 6 and paragraph 214), the surface being opposite to a surface on a side to which the first semiconductor substrate is bonded (the interlayer insulating films 222 is shown on the top surface of the semiconductor layer 200S and the first substrate 100 is shown on the bottom surface of semiconductor layer 200S in Fig. 6); and
forming a through electrode (a through electrode TGV) that penetrates the second semiconductor substrate from the interlayer film side and is electrically connected to the first semiconductor substrate (the through electrode TGV is shown penetrating from the interlayer insulating films 222 to the first substrate 100 in Fig. 6) (Fig. 6, Fig. 14A and paragraph 153),
wherein the through electrode includes a lower electrode provided from substantially the same height as a surface of the second semiconductor substrate on the interlayer film side toward the second semiconductor substrate (a portion of the through electrode TGV starting at the surface of the semiconductor layer 200S functions as the lower electrode and is shown in annotated Fig. 14A below), and an upper electrode penetrating the interlayer film and connected to the lower electrode (a portion of the through electrode TGV starting above the surface of the semiconductor layer 200S functions as the upper electrode and is shown connected to the lower portion in annotated Fig. 14A below).
In regard to claim 10, Saka teaches an electronic device (an automobile) including a solid-state imaging element (an imaging device) (Fig. 1, Fig. 74 and paragraphs 116 and 354), the solid-state imaging element, comprising:
a first semiconductor substrate (a first substrate 100) provided with a photodiode (photodiode PD) and some pixel transistors (transfer transistor TR) for each pixel (the first substrate 100 is provided with the plurality of pixels 541A, 541B, 541C, and 541D, and each of these pixels 541 includes a photodiode PD) (Fig. 6 and paragraphs 132 and 140);
a second semiconductor substrate (a semiconductor layer 200S of a second substrate 200) bonded to the first semiconductor substrate and provided with another pixel transistor (pixel circuit 210) other than the some pixel transistors constituting the pixel (the first substrate 100, the second substrate 200, and the third substrate 300 are bonded together and the pixel circuit 210 provided to the semiconductor layer 200S and is alternatively referred to as pixel transistor circuit) (Fig. 6, paragraphs 131-132 and 176);
an interlayer film (interlayer insulating films 222) stacked on a surface (top surface) of the second semiconductor substrate via an insulating film (the interlayer insulating film 222 is shown on the semiconductor layer 200S via a passivation film 221 in Fig. 6) (Fig. 6 and paragraph 214), the surface being opposite to a surface on a side to which the first semiconductor substrate is bonded (the interlayer insulating films 222 is shown on the top surface of the semiconductor layer 200S and the first substrate 100 is shown on the bottom surface of semiconductor layer 200S in Fig. 6); and
a through electrode (a through electrode TGV) that penetrates the second semiconductor substrate from the interlayer film side and is electrically connected to the first semiconductor substrate (the through electrode TGV is shown penetrating from the interlayer insulating films 222 to the first substrate 100 in Fig. 6) (Fig. 6, Fig. 14A and paragraph 153),
wherein the through electrode includes a lower electrode provided from substantially the same height as a surface of the second semiconductor substrate on the interlayer film side toward the second semiconductor substrate (a portion of the through electrode TGV starting at the surface of the semiconductor layer 200S functions as the lower electrode and is shown in annotated Fig. 14A below), and an upper electrode penetrating the interlayer film and connected to the lower electrode (a portion of the through electrode TGV starting above the surface of the semiconductor layer 200S functions as the upper electrode and is shown connected to the lower portion in annotated Fig. 14A below).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Saka as applied to claim 1 above, in view of Nakazawa et al. (WO 2020262643 A1; hereinafter “Nakazawa”), US 2022/0271070 A1 is used as a translation for WO 2020262643 A1.
In regard to claim 2, Saka doesn’t explicitly teach wherein an insulating layer is provided between the lower electrode and the second semiconductor substrate.
Nakazawa teaches a solid-state imaging element (a solid-state imaging device 1) (Fig. 3 and paragraph 214), wherein an insulating layer (an oxide film 120D) is provided between a lower electrode (a portion of the through electrode 120E including the pad section 120 below a wiring layer 200T) and a second semiconductor substrate (the oxide film 120D is shown between the portion of the through electrode 120E below a wiring layer 200T and a semiconductor layer 200S in Fig. 90) (Fig. 90 and paragraphs 229).
It would have been obvious to one skilled in the art to combine the teachings of Saka with Nakazawa to have an insulating layer provided between the lower electrode and the second semiconductor substrate since it is well known that insulation structures are used to provide increased short protection within the device.
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In regard to claim 4, Saka doesn’t explicitly teach wherein a diameter of the lower electrode is larger than a diameter of the upper electrode of the lower electrode.
Nakazawa teaches wherein a diameter of the lower electrode is larger than a diameter of the upper electrode of the lower electrode (a pad section 120 of the lower electrode is shown to have a larger diameter than the through electrode 120E as it contains 120R which is also described as having a larger diameter than the through electrode 120E in Fig. 90) (Fig. 90 and paragraphs 261 and 467).
It would have been obvious to one skilled in the art to combine the teachings of Saka with Nakazawa to have a diameter of the lower electrode is larger than a diameter of the upper electrode since this allows for the device to have a smaller circuit footprint as described by Nakazawa (paragraph 261).
In regard to claim 8, doesn’t explicitly teach wherein the lower electrode is configured in a staircase shape in which at least a part of a diameter is different from a diameter of another part.
Nakazawa teaches wherein the lower electrode is configured in a staircase shape in which at least a part of a diameter is different from a diameter of another part (a pad section 120 of the lower electrode is shown to have a larger diameter than the through electrode 120E giving the lower electrode portion of the through electrode 120E a staircase shape as shown in annotated Fig. 90 above).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hiramatsu et al (WO 2020262131 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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/SEYON ALI-SIMAH PUNCHBEDDELL/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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