DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 09/11/2024 and 02/09/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claim 6 is objected to because of the following informalities: Line 25, the [[or]] in “flight or each” should be “for”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5-6 are is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by K. Yasutomi, Y. Okura, K. Kagawa and S. Kawahito, "A Sub-100 μ m-Range-Resolution Time-of-Flight Range Image Sensor With Three-Tap Lock-In Pixels, Non-Overlapping Gate Clock, and Reference Plane Sampling," in IEEE Journal of Solid-State Circuits, vol. 54, no. 8, pp. 2291-2303, Aug. 2019, doi: 10.1109/JSSC.2019.2916310. keywords: {Logic gates;Image resolution;Clocks;Photoconductivity;Modulation;Calibration;Electric potential;CMOS image sensor (CIS);delay-locked loop (DLL)-based skew calibration;high range resolution;lateral electric field modulator (LEFM);lock-in pixel;non-overlapping gate clock;photogenerated-charge partitioning;range imaging;reference plane sampling (RPS);skew calibration;time-of-flight (TOF)}, referred to as YASUTOMI hereinafter.
Regarding Claim 1, YASUTOMI shows a distance measuring device (Abstract, Sections I & II disclose a TOF range imager / distance measuring system for 3-D scanning and distance measurement.) comprising:
a light source configured to generate pulsed light (Abstract; Section II-A states a short-pulse laser with ~100 ps pulse width is used as the light source.);
a light source control circuit configured to control a generation timing of the pulsed light (Section III-E; Section IV describes a prototype chip producing the laser-emission trigger and using a digital delay generator to precisely control trigger delay.);
a plurality of pixels arranged two-dimensionally (Abstract; Section III-A; Section IV), each of the pixels having a photoelectric conversion region configured to convert light into a charge (Section III-B; Appendix discloses a pinned photodiode (PPD) / photodiode-based lock-in pixel that converts incident light into photocurrent and accumulated charge.), a plurality of charge readout regions provided close to the photoelectric conversion region and spaced apart from each other (Section II-B; Section III-B discloses three floating diffusion (FD) nodes (FD1–FD3) used to store/read out signal charge, separate from each other and associated with the photodetection structure.), and a plurality of control electrodes that are respectively provided to correspond to the photoelectric conversion region and the plurality of charge readout regions and configured to apply a plurality of control pulses for charge transfer between the photoelectric conversion region and the plurality of charge readout regions (Section II-B; Section III-B discloses gates G1–G3 and GD that modulate the potential and transfer/route photogenerated charges to respective FDs during time windows TW1–TW3.);
a control signal generating circuit configured to generate the plurality of control pulses to be applied to the plurality of pixels (Section III-C; Section III-D discloses a pattern generator (PG) producing gating clocks G1(i)–G3(i) and GD(i).);
a plurality of driver circuits configured to respectively apply the plurality of control pulses generated by the control signal generating circuit to the plurality of control electrodes of a plurality of pixel groups divided from the plurality of pixels (Section III-A; Section III-C; Fig. 5; Fig. 7 disclose column-parallel gating clock drivers that drive gate clocks in each column/pixel group. The pixels are effectively divided by columns and driven in parallel.);
a reference signal generating circuit configured to generate a reference pulse based on the plurality of control pulses generated by the control signal generating circuit (Section III-C; Section III-E; Fig. 8; Fig. 10 discloses a reference column / reference clock G1REF and reference pixel array used to sample correlated jitter. A reference pulse is derived from the gating clock system.);
a plurality of time difference information generating circuits provided to correspond to the plurality of driver circuits and configured to generate time difference information corresponding to a time difference between one of the plurality of control pulses applied by each of the plurality of driver circuits and the reference pulse (Abstract; Section III-E; Fig. 10; Eq. (5) disclose reference plane sampling (RPS) to cancel correlated jitter by comparing main-pixel TOF timing with reference-pixel timing. It uses reference pixels and averaging.);
and a calculation processor configured to calculate time information corresponding to a light time of flight for each of the plurality of pixels based on a plurality of charge amounts that are amounts of charges accumulated in the plurality of charge readout regions of the plurality of pixels (Section II-C; Appendix; Eq. (1), (11), (12) explicitly calculates TOF/distance from the charge amounts N1, N2, N3 using the signal charge ratio X and the TOF equation.), wherein the calculation processor deletes a jitter component from the time information calculated for the pixel group by using a plurality of pieces of the time difference information generated by the plurality of time difference information generating circuits (Abstract; Section III-E; Eq. (5) RPS cancels correlated jitter using reference pixels. This is a functional and conceptual match to jitter deletion using reference-based time difference information.).
Regarding claim 2, YASUTOMI shows the limitations as per Claim 1 above, wherein the calculation processor calculates an average value of the plurality of pieces of time difference information generated by the plurality of time difference information generating circuits (Section III-E; Eq. (5)), and deletes the jitter component from the time information by subtracting a difference between the time difference information generated by the time difference information generating circuit corresponding to the pixel group and the average value from the time information calculated for the pixel group (Eq. (5); Section III-E discloses subtracting the average reference TOF and adding the known reference TOF: ttof,calc(i,j)=ttof(i,j)-avg(tref)+tref,known. This is very close to the claimed correction logic.).
Regarding claim 3, YASUTOMI shows the limitations as per Claim 1 above, wherein the time difference information generating circuit includes a pseudo pixel having the photoelectric conversion region, the plurality of charge readout regions, and the plurality of control electrodes (Section III-E; Fig. 10 uses a reference pixel array embedded in the same focal plane. While not expressly using the same language as that in the instant disclosure, the concept is functionally similar to a pseudo pixel/reference pixel and therefore, for purposes of examination will be treated as being anticipated.), supplies a charge in a pseudo manner according to a timing of the reference pulse to the photoelectric conversion region of the pseudo pixel, and calculates the time information as the time difference information based on a plurality of charge amounts that are amounts of charges accumulated in the plurality of charge readout regions of the pseudo pixel based on the plurality of control pulses applied by the corresponding driver circuit (Section III-E; Fig. 10 reference plane sampling causes the reference pixels to measure a known-distance reflection using the same trigger/timing chain. Again, while the art does not literally describe supplying a charge in a pseudo manner, the examiner is interpreting the operation as being functionally analogous to, and thus anticipatory of, the claimed limitation.).
Regarding claim 5, YASUTOMI shows the limitations as per Claim 1 above, wherein the time difference information generating circuit includes a time measurement circuit that generates a time difference between one of the plurality of control pulses and the reference pulse as the time difference information (Section III-C; Fig. 7; Fig. 8 discloses a bang-bang phase detector (BPD) and delay-line/DLL calibration circuit comparing G1(i) with G1REF to measure phase difference. This is analogous to a time measurement circuit measuring a pulse difference.).
Regarding Claim 6, YASUTOMI shows a distance measuring method comprising:
controlling, by a light source control circuit, a light source to generate pulsed light (Abstract; Section II-A states a short-pulse laser with ~100 ps pulse width is used as the light source.);
generating, by a control signal generating circuit, for a plurality of two-dimensionally arranged pixels, a plurality of control pulses to be applied to the plurality of pixels (Section III-C; Section III-D; Fig. 7 discloses a pattern generator generating gating clocks for the pixel array.), each of the pixels having a photoelectric conversion region configured to convert light into a charge (Section III-B; Appendix discloses a pinned photodiode (PPD) / photodiode-based lock-in pixel that converts incident light into photocurrent and accumulated charge.), a plurality of charge readout regions provided close to the photoelectric conversion region and spaced apart from each other (Section II-B; Section III-B discloses three floating diffusion (FD) nodes (FD1–FD3) used to store/read out signal charge, separate from each other and associated with the photodetection structure.), and a plurality of control electrodes that are respectively provided to correspond to the photoelectric conversion region and the plurality of charge readout regions and configured to apply the plurality of control pulses for charge transfer between the photoelectric conversion region and the plurality of charge readout regions (Section II-B; Section III-B discloses gates G1–G3 and GD that modulate the potential and transfer/route photogenerated charges to respective FDs during time windows TW1–TW3.);
applying, by a plurality of driver circuits, the plurality of control pulses generated by the control signal generating circuit to the plurality of control electrodes of a plurality of pixel groups divided from the plurality of pixels (Section III-A; Section III-C describes column-parallel drivers driving the gate clocks in each column/pixel group.);
generating, by a reference signal generating circuit, a reference pulse based on the plurality of control pulses generated by the control signal generating circuit (Section III-C; Section III-E; Fig. 8; Fig. 10 discloses a reference column / reference clock G1REF and reference pixel array used to sample correlated jitter. A reference pulse is derived from the gating clock system.);
generating, by a plurality of time difference information generating circuits provided to correspond to the plurality of driver circuits, time difference information corresponding to a time difference between one of the plurality of control pulses applied by each of the plurality of driver circuits and the reference pulse (Abstract; Section III-E; Fig. 10; Eq. (5) disclose reference plane sampling (RPS) to cancel correlated jitter by comparing main-pixel TOF timing with reference-pixel timing. It uses reference pixels and averaging.);
and calculating, by a calculation processor, time information corresponding to a light time of flight or each of the plurality of pixels based on a plurality of charge amounts that are amounts of charges accumulated in the plurality of charge readout regions of the plurality of pixels (Section II-C; Appendix; Eq. (1), (11), (12) explicitly calculates TOF/distance from the charge amounts N1, N2, N3 using the signal charge ratio X and the TOF equation.), wherein in calculating the time information, a jitter component is deleted from the time information calculated for the pixel group by using a plurality of pieces of the time difference information generated by the plurality of time difference information generating circuits (Abstract; Section III-E; Eq. (5) RPS cancels correlated jitter using reference pixels. This is a functional and conceptual match to jitter deletion using reference-based time difference information.).
Allowable Subject Matter
Claim4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please see the Notice of References Cited, form PTO-892 for discovered references deemed relevant but not material to patentability.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUSTIN W. RIDER whose telephone number is (571)270-1068. The examiner can normally be reached Monday-Friday, 7.00 am - 4.30 pm.
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JUSTIN W. RIDER
Primary Patent Examiner
Art Unit 2486
/Justin W Rider/Primary Patent Examiner, Art Unit 2486
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