DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Europe on 02/04/2022. A certified copy of the EP22155104.7 application was received 08/02/2024.
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statement filed 08/02/2024 have all been considered and made of record.
Joint Inventors
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-6, 9, and 14-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regards to claim 2, the claim recites “…wherein one or more elements or one or more groups of elements of the capacitor have the same form as an element or a group of elements of the transducer…”. The phrase “…have the same form…” implies the existence of a comparative relationship between the “one or more elements or one or more groups of elements of the capacitor” and the “element or a group of elements of the transducer” but does not define said relationship. For example, it is unclear if the “one or more groups of elements” must be made of the same materials, must have the same geometric shape, must appear the same the same to an observer, and/or share some other commonality as the “element or a group of elements of the transducer”. The claim is indefinite because the limitations create confusion regarding the structure of the claimed device.
Examiner’s note: For the purposes of further examination, examiner will generally interpret at least some elements of the capacitor of the claimed device as having a similar shape to at least some elements of the transducer of the claimed device.
With regards to claim 3, the claim recites “…wherein a group of elements of the transducer includes a waveguide arranged between two electrodes…”. It is unclear whether or not the two electrodes are part of the transducer. It is understood by examiner that transducers commonly comprise electrodes, but it is unclear of the “two electrodes” of claim 3 are electrodes within the transducer, or other additional electrodes outside of the transducer elsewhere within the integrated circuit. The claim is indefinite because the limitations create confusion regarding the structure of the claimed device.
Examiner’s note: For the purposes of further examination, examiner will generally interpret the group of elements of the transducer of the claimed device as being between two electrodes within the claimed device.
With regards to claim 4, the claim recites “…wherein a group of elements of the transducer includes a doped silicon element supporting an electrode…” It is unclear whether or not the electrode is part of the transducer. It is understood by examiner that transducers commonly comprise electrodes, but it is unclear if the “electrode” of claim 4 is an electrode within the transducer, or another electrodes outside of the transducer elsewhere within the integrated circuit. The claim is indefinite because the limitations create confusion regarding the structure of the claimed device.
Examiner’s note: For the purposes of further examination, examiner will generally interpret the group of elements of the transducer as supporting an electrode within the claimed device.
With regards to claim 5, the claim recites “…wherein a group of elements of the transducer includes a nonlinear element arranged between two electrodes…”. It is unclear whether or not the two electrodes are part of the transducer. It is understood by examiner that transducers commonly comprise electrodes, but it is unclear if the “two electrodes” of claim 5 are electrodes within the transducer, or other additional electrodes outside of the transducer, elsewhere within the integrated circuit. The claim is indefinite because the limitations create confusion regarding the structure of the claimed device.
Examiner’s note: For the purposes of further examination, examiner will generally interpret the group of elements of the transducer of the claimed device as being between two electrodes within the claimed device.
With regards to claim 6, the claim recites “…wherein a group of elements of the transducer includes a doped region of the substrate arranged between two electrodes…” It is unclear whether or not the two electrodes are part of the transducer. It is understood by examiner that transducers commonly comprise electrodes, but it is unclear if the “two electrodes” of claim 6 are electrodes within the transducer, or other additional electrodes outside of the transducer, elsewhere within the integrated circuit. Furthermore, it is unclear if the term “…nonlinear element…” is referring to an element with a nonlinear shape (I.E, a bent portion of a circuit between the two electrodes), an element made of a material with a non-proportional stress-strain relationship, an element capable of conducting a non-linear signal, or some other interpretation. The claim is indefinite because the limitations create confusion regarding the structure of the claimed device.
Examiner’s note: For the purposes of further examination, examiner will generally interpret the group of elements of the transducer of the claimed device as being between two electrodes within the claimed device and will interpret the non-linear element of the claimed device as having a non-linear shape.
With regards to claim 9, the claim recites “…wherein the same level of the at least one electrically conductive element of the transducer respectively of the capacitor is defined with respect to the first level of the substrate respectively with respect to the second level of the substrate…”. At least one of above uses of “respectively”, “with respect to”, and “respectfully with respect to” are grammatically incorrect. The above limitations appear to be establishing some physical relationship between the conductive element, capacitor, first substrate level, and second substrate level, but the nature of this relationship is unclear due. The claim is indefinite because the limitations create confusion regarding the structure of the claimed device.
Examiner’s note: For the purposes of further examination, examiner will generally interpret the conductive element, capacitor, first substrate level, and second substrate level as being physically coupled.
With regards to claim 14, the claim recites “…a method for fabricating an integrated circuit …wherein a transducer and a capacitor are arranged on the substrate using a single fabrication process…”. The claim does not define what does or does not constitute a “single fabrication process”. Any given integrated circuit could be considered as being fabricated through a single fabrication process or numerous fabrication processes. The instant specification states “…the single fabrication process includes one or more of a deposition process, a patterning process, an etching process, and a doping process…”. The claim is indefinite because the limitations create confusion regarding the bounds of the claimed method.
Examiner’s note: For the purposes of further examination, examiner will interpret the claimed device as having multiple tiered regions.
Claim 15 inherits the indefiniteness of claim 14 on which it depends.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, and 8-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yap (US 5611008 A).
With regards to claim 1, Yap discloses an integrated circuit, comprising: a substrate which supports an electrooptic or optoelectric transducer and a capacitor (Substrate [elements 41 and 50], capacitor 65, transducer [elements 24, 42, 43, 90, 92, and 93]), wherein at least one electrically conductive element of the transducer and at least one electrically conductive element of the capacitor are arranged at the same level with respect to the substrate (Conductive elements 84 and 86, and level [region between elements 41 and 24]).
With regards to claim 2, Yap discloses the integrated circuit of claim 1, wherein one or more elements or one or more groups of elements of the capacitor have the same form as an element or a group of elements of the transducer (Fig1/Form of electrically conductive elements 84 and 86).
With regards to claim 3, Yap discloses the integrated circuit of claim 1, wherein a group of elements of the transducer includes a waveguide arranged between two electrodes (Fig1/Waveguide 42 and electrodes 84).
With regards to claim 5, Yap discloses the integrated circuit of claim 1, wherein a group of elements of the transducer includes a nonlinear element arranged between two electrodes (Fig1/Nonlinear elements 90).
With regards to claim 8, Yap discloses the integrated circuit of claim 1, wherein the transducer includes a photonic waveguide (Fig1/Photonic waveguide 42).
With regards to claim 9, Yap discloses the integrated circuit of claim 1, wherein the substrate includes an area at a first level for supporting the transducer and an area at a second level different from the first level for supporting the capacitor (Fig1/First level 52 and second level [upper surface of element 50]), and wherein the same level of the at least one electrically conductive element of the transducer respectively of the capacitor is defined with respect to the first level of the substrate respectively with respect to the second level of the substrate (Fig1).
With regards to claim 10, Yap discloses the integrated circuit of claim 1, wherein the at least one electrically conductive element of the transducer includes a first electrode and the at least one electrically conductive element of the capacitor includes a coupled capacitor plate, wherein a part of the coupled capacitor plate coincides with the first electrode (Figs1-5/First electrode [electrical contact between elements 24 and 84]; Column 7/Lines 13-20).
With regards to claim 11, Yap discloses the integrated circuit of claim 1, wherein the capacitor includes a coupled capacitor plate for coupling with the transducer and a decoupled capacitor plate for receiving a high-frequency signal (Fig5/Coupled capacitor plate 115 and decoupled capacitor plate 116).
With regards to claim 12, Yap discloses the integrated circuit of claim 1, wherein the capacitor has the form of a finger capacitor (Fig5).
With regards to claim 13, Yap discloses the integrated circuit of claim 1, wherein the substrate further supports an inductor having one end for coupling with the transducer and another end for receiving a low-frequency or direct current signal (Yap/Fig1/Inductor 64; Column 4/Lines 62-66).
With regards to claim 14, Yap discloses a method for fabricating an integrated circuit, wherein a substrate is provided, and wherein a transducer and a capacitor are arranged on the substrate using a single fabrication process, wherein at least one electrically conductive element of the transducer and at least one electrically conductive element of the capacitor are arranged at the same level with respect to the substrate (Fig1/Substrate 41, transducer [elements 24, 42, 43, 90, 92, and 93], capacitor 65, conductive elements 84 and 86, and level [region between elements 41 and 24]).
With regards to claim 15, Yap discloses the method of claim 14, wherein an inductor is arranged on the substrate using the single fabrication process (Yap/Fig1/Inductor 64).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yap (US 5611008 A).
With regards to claim 4, Yap discloses the integrated circuit of claim 1 wherein elements of the transducer support an electrode, but is silent regarding whether or not elements of the transducer include a doped silicon element. However, it would have been obvious the use doped silicon within the transducer of Yap since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice (In re Leshin, 125 USPQ 416), and purposeful application of impurities (doping) is a well-known method for modifying the electrical and/or photovoltaic properties of silicon.
With regards to claim 6, Yap discloses the integrated circuit of claim 1 wherein elements of the transducer are arranged between two electrodes, but is silent regarding whether or not a elements of the transducer include a doped region of the substrate. However, it would have been obvious to use doped silicon within the transducer of yap since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice (In re Leshin, 125 USPQ 416), and purposeful application of impurities (doping) is a well-known method for modifying the electrical and/or photovoltaic properties of silicon.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yap (US 5611008 A) as applied to claim 1 above, in view of Nissala (US 20230239054 A1).
With regards to claim 7, Yap discloses the integrated circuit of claim 1, but is silent regarding the transducer including a plasmonic waveguide. However, the practice of configuring a transducer to include a plasmonic waveguide exists in the art as exemplified by Nissala.
Yap discloses an optoelectronic circuit with transducer wherein the transducer is a photodetector. Nissala discloses an optoelectronic circuit with transducer wherein the transducer is a plasmonic photodetector (Nissala/Paragraph 60). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the photodetector of Yap as a plasmonic photodetector as suggested by Nissala since doing so would facilitate compact transducer architecture.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marc E Manheim whose telephone number is (703)756-1873. The examiner can normally be reached 6:30am - 5pm E.T., Monday - Tuesday and Thursday - Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MARC E MANHEIM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
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