Prosecution Insights
Last updated: October 25, 2026
Application No. 18/835,797

COMMUNICATION SYSTEM, RECEIVER, EQUALIZATION SIGNAL PROCESSING CIRCUIT, METHOD, AND COMPUTER READABLE MEDIUM

Final Rejection §103
Filed
Aug 05, 2024
Priority
Feb 25, 2022 — nonprovisional of PCTJP2022007907
Examiner
SANCHEZ, DIBSON J
Art Unit
2634
Tech Center
2600 — Communications
Assignee
NEC Corporation
OA Round
2 (Final)
74%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
399 granted / 540 resolved
+11.9% vs TC avg
Strong +23% interview lift
Without
With
+22.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
16 currently pending
Career history
560
Total Applications
across all art units

Statute-Specific Performance

§101
3.0%
-37.0% vs TC avg
§103
63.8%
+23.8% vs TC avg
§102
6.4%
-33.6% vs TC avg
§112
26.4%
-13.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 540 resolved cases

Office Action

§103
DETAILED ACTION This Office Action is in response to the Applicant’s communication filed on 8/11/2026. In virtue of this communication claims 1-18 are currently pending in the instant application. Response to Amendment In response to the action mailed on 5/12/2026, the Applicant has filed a response without amending the claims. Response to Arguments The Applicant’s arguments have been fully considered but they are not persuasive. The Applicant argues that the combination would not achieve the claimed subject matter. The Applicant argues that the filters of Yadav correspond to filters 172, 173, 174, 176, 177 and 178 illustrated in Fig 4 of the non-limiting application. On the other hand, the present application relates to the part corresponding to 171 and 179 (and the associated method of coefficient updating 177). However, the Examiner respectfully disagrees with this statement because of the following. First, limitations from the Applicant’s specification are not read into the claims. See MPEP 2145 section “Arguing Limitations Which Are Not Claimed” for details. Therefore, any difference between the cited prior art and the instant application must be clearly recited in the independent claims in order to have any weight and/or patentable consideration. Second, Yadav teaches what is currently required by the present claims and is the opposite of what the Applicant argues. More specifically Yadav Fig 1(a) teaches the first filter (2x2 MIMO filter) and the filter group (M-WL-CMA) that is required by the claims (see rejection below for details). There is nothing in the claims that prevents the Examiner from taking this interpretation and making this rejection. Here, the terms “first filter” and “filter group” i.e. as currently presented in the claims are recited in a broad manner and have other interpretations different from Fig 4 of the Applicant’s disclosure. The Applicant argues that Yadav's structure is fundamentally different. The Applicant argues that Yadav fails to teach/suggest that the reception signal that is subjected to compensation for the distortion and its complex conjugate are being input to the following filter group. However, the Examiner respectfully disagrees with this statement because Yadav teaches clearly this limitation. More specifically, Yadav Fig 1(a) teaches the reception signal (e.g. Xin or Yin) and the complex conjugate signal (e.g. from [ ]*) that are subjected to compensation for the first distortion (i.e. from the first filter (2x2 MIMO filter)) being input to the filter group (M-WL-CMA) that includes a second filter (e.g. FIR filter αx or FIR filter αy). See diagram below for details. Thus, Yadav teaches this argued features i.e. as currently presented in the claims and is contrary to what the Applicant argues. PNG media_image1.png 435 745 media_image1.png Greyscale The Applicant argues that the proposed modification would not work successfully. The Applicant argues that regarding Zhou adaptively updating coefficients based on the difference between the output signal and a predetermined value does not mean that adaptation can always be applied to any filter configuration and will work successfully. However, the Examiner respectfully disagrees with this statement because of the following. First, there is no bodily incorporation of the secondary reference of Zhou into the primary reference of Yadav, but rather it is the system of Yadav that is combined with the teachings of the system of Zhou i.e. in order to better clarify the operation/ configuration of the system of Yadav. As a reminder, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference, but rather, the test for obviousness is what the combined teachings of the references suggest to those of ordinary skill in the art. See MPEP 21445 section “Arguing That Prior Art Devices Are Not Physically Combinable” for details. In this case, the combination of Yadav and Zhou was simply made to better show and illustrate that the equalization circuit as described in Yadav which adaptively controls filter coefficients in a feedback manner comprises a known memory and a known processor (i.e. as described in Zhou Fig 3, Fig 6, Fig 7) (see rejection below for details). Here, the combination does not change the principle of operation of the system of Yadav. Thus, the combination of Yadav and Zhou is proper and is the opposite to what the Applicant argues. In conclusion, for at least these reasons, the cited prior art still teaches the claims i.e. as currently being presented. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1, 3-4, 6 and 10-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yadav et al (Modified Widely Linear Filter for Simultaneous Multi-impairment Compensation) in view of Zhou et al (US Pub 20130138375). Regarding claim 1. Yadav discloses an equalization signal processing circuit comprising: a first filter configured to perform compensation for first distortion being included in a reception signal being acquired by coherent-receiving a signal being transmitted from a transmitter via a transmission path, with respect to the reception signal and a complex conjugate signal of the reception signal, and output the reception signal and the complex conjugate signal that are subjected to compensation for the first distortion (Fig 1(a), where an equalization circuit comprises a first filter (2x2 MIMO filter) configured to perform compensation for first distortion being included in a reception signal (e.g. Xin or Yin) acquired by coherent-receiving a signal being transmitted from a transmitter via a transmission path (as shown in Fig 1(b)), with respect to the reception signal (e.g. Xin or Yin) and a complex conjugate signal (e.g. from [ ]*) of the reception signal (e.g. Xin or Yin), and output the reception signal (e.g. Xin or Yin) and the complex conjugate signal (e.g. from [ ]*) that are subjected to compensation for the first distortion); a filter group including a second filter configured to receive, as input signals, the reception signal and the complex conjugate signal that are subjected to compensation for the first distortion, perform compensation for second distortion being included in the reception signal, and output the reception signal being subjected to compensation for the second distortion (Fig 1(a), where the equalization circuit comprises a filter group (M-WL-CMA) that includes a second filter (e.g. FIR filter αx or FIR filter αy) configured to receive, as input signals, the reception signal (e.g. Xin or Yin) and the complex conjugate signal (e.g. from [ ]*) that are subjected to compensation for the first distortion, perform compensation for second distortion being included in the reception signal (e.g. Xin or Yin), and output the reception signal (e.g. Xin or Yin) being subjected to compensation for the second distortion); and adaptively controlling a filter coefficient of the second filter, based on a difference between an output signal being output from the filter group and a predetermined value of the output signal (Fig 1(a), where the equalization circuit adaptively controls (e.g. via an error calculation) a filter tap/coefficient of the second filter (e.g. FIR filter αx or FIR filter αy) based on a difference between an output signal (e.g. Xout or Yout) output from the filter group (M-WL-CMA) and a predetermined value (e.g. Rx/y) of the output signal (e.g. Xout or Yout) (see equation (1))). Yadav fails to explicitly disclose the equalization circuit comprises at least one memory storing instructions; and at least one processor configured to execute the instructions. However, Zhou discloses an equalization circuit comprises at least one memory storing instructions and at least one processor configured to execute the instructions (Fig 3, Fig 6, Fig 7, where an equalization circuit (330) (which adaptively controls filter coefficients in a feedback manner) comprises at least one memory storing instructions and at least one processor configured to execute the instructions (i.e. at computer 704)). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teachings of the equalization circuit as described in Yadav, with the teachings of the equalization circuit (330) as described in Zhou. The motivation being is that as shown an equalization circuit (330) (which adaptively controls filter coefficients in a feedback manner) comprises at least one memory and at least one processor and one of ordinary skill in the art can implement this concept into the equalization circuit as described in Yadav and better show and illustrate that the equalization circuit (which adaptively controls filter coefficients in a feedback manner) comprises at least one memory and at least one processor i.e. because the equalization circuit uses a memory and a processor in order to optimally perform calculations and computations and where such calculations and computations are used to optimally perform signal equalization and which combination is being made because the systems are similar and have overlapping components (e.g. equalization circuits,…) and which combination is a simple implementation of a known concept of a known equalization circuit (330) into another similar equalization circuit, namely, for better clarifying its operation/ configuration and which combination yields predictable results. Regarding claim 3. Yadav as modified by Zhou also discloses the equalization signal processing circuit, wherein the second distortion includes in-receiver distortion occurring in a receiver, and the second filter compensates for in-receiver distortion (Yadav Fig 1(a), where the second distortion includes in-receiver distortion (e.g. phase noise) occurring in a receiver, and the second filter (e.g. FIR filter αx or FIR filter αy) compensates for in-receiver distortion (e.g. phase noise) (paras [2][3])). Regarding claim 4. Yadav as modified by Zhou also discloses the equalization signal processing circuit, wherein the first filter includes a complex signal input complex coefficient filter having a predetermined tap length, and the second filter includes a multiple input single output (MISO) filter (Yadav Fig 1(a), where the first filter (2x2 MIMO filter) includes a complex signal input (i.e. due to real and imaginary parts) complex coefficient filter having a predetermined tap length (i.e. at 2x2 MIMO filter), and the second filter (e.g. FIR filter αx or FIR filter αy) includes a multiple input single output (MISO) filter). Regarding claim 6. Yadav as modified by Zhou also discloses the equalization signal processing circuit, wherein the signal being transmitted from the transmitter is a polarization multiplexed signal, and the first filter and the second filter are arranged for each polarization (Yadav Fig 1(a), Fig 1(b), where the signal transmitted from the transmitter (as shown in Fig 1(b)) is a polarization multiplexed signal (i.e. due to X, Y polarizations), and the first filter (2x2 MIMO filter) and the second filter (e.g. FIR filter αx or FIR filter αy) are arranged for each polarization). Regarding claim 10. Yadav as modified by Zhou also discloses a receiver comprising: a receiving circuit configured to coherent-receive a signal being transmitted from a transmitter via a transmission path; and the equalization signal processing circuit (Yadav Fig 1(a), Fig 1(b), where a receiving circuit (Receiver) is configured to coherent-receive a signal being transmitted from a transmitter via a transmission path (as shown in Fig 1(b)) and comprises the equalization circuit). Regarding claim 11. Claim 11 is similar to claim 2, therefore, claim 11 is rejected for the same reasons as claim 2. Regarding claim 12. Claim 12 is similar to claim 3, therefore, claim 12 is rejected for the same reasons as claim 3. Regarding claim 13. Claim 13 is similar to claim 4, therefore, claim 13 is rejected for the same reasons as claim 4. Regarding claim 14. Yadav as modified by Zhou also discloses a communication system comprising: a transmitter configured to transmit a signal via a transmission path; and the receiver (Yadav Fig 1(a), Fig 1(b), where a communication system comprises a transmitter configured to transmit a signal via a transmission path (as shown in Fig 1(b)) and comprises the receiver (Receiver)). Regarding claim 15. Claim 15 is similar to claim 2, therefore, claim 15 is rejected for the same reasons as claim 2. Regarding claim 16. Claim 16 is similar to claim 3, therefore, claim 16 is rejected for the same reasons as claim 3. Regarding claim 17. Claim 17 is similar to claim 1, therefore, claim 17 is rejected for the same reasons as claim 1. Regarding claim 18. Claim 18 is similar to claim 1, therefore, claim 18 is rejected for the same reasons as claim 1. Claim 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yadav et al (Modified Widely Linear Filter for Simultaneous Multi-impairment Compensation) in view of Zhou et al (US Pub 20130138375) in further view of Venktasubramani et al (IQ Skew Tolerance Study of Modified Widely Linear Filter in 400 Gbps PM-16QAM System). Regarding claim 7. Yadav as modified by Zhou also discloses the equalization signal processing circuit, and the at least one processor configured to execute the instructions to adaptively control the filter coefficient of the second filter by using an error back propagation method (Yadav Fig 1(a), where the equalization circuit adaptively controls the filter tap/coefficient of the second filter (e.g. FIR filter αx or FIR filter αy) by using an error back propagation method (i.e. as shown in Fig 1(a) and equation (1)). Yadav as modified by Zhou fails to explicitly disclose the filter group includes one or more filters being connected in series along a signal path of the reception signal, on a downstream side with respect to the second filter. However, Venktasubramani discloses a filter group includes one or more filters being connected in series along a signal path of a reception signal, on a downstream side with respect to a second filter (Fig 1(a), where a filter group includes one or more filters (e.g. WL-DFE) connected in series along a signal path of a reception signal, on a downstream side with respect to a second filter (e.g. FIR filter αx or FIR filter αy)). Therefore, it would have been obvious to one of ordinary skill in the art to modify the second filter (e.g. FIR filter αx or FIR filter αy) as described in Yadav as modified by Zhou, with the teachings of the second filter (e.g. FIR filter αx or FIR filter αy) as described in Venktasubramani. The motivation being is that as shown one or more filters (e.g. WL-DFE) can be on a downstream side of a second filter (e.g. FIR filter αx or FIR filter αy) and one of ordinary skill in the art can implement this concept into the second filter (e.g. FIR filter αx or FIR filter αy) as described in Yadav as modified by Zhou and have one or more filters (e.g. WL-DFE) be on a downstream side of the second filter (e.g. FIR filter αx or FIR filter αy) i.e. as an alternative so as to have the second filter (e.g. FIR filter αx or FIR filter αy) with a known technique of a known second filter (e.g. FIR filter αx or FIR filter αy) for the purpose of optimally adding an additional filter (e.g. WL-DFE) in order to compensate for transmitter imbalance and which modification is being made because the systems are similar and have overlapping components (e.g. FIR filters αx and FIR filters αy) and which modification is a simple implementation of a known concept of a known second filter (e.g. FIR filter αx or FIR filter αy) into another similar second filter (e.g. FIR filter αx or FIR filter αy), namely, for its improvement and for optimization and which modification yields predictable results. Allowable Subject Matter Claims 2, 5, and 8-9 is/are still objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIBSON J SANCHEZ whose telephone number is (571)272-0868. The examiner can normally be reached on Mon-Fri 10:00-6:00. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Kenneth Vanderpuye can be reached on 5712723078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DIBSON J SANCHEZ/ Primary Examiner, Art Unit 2636
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Prosecution Timeline

Aug 05, 2024
Application Filed
May 12, 2026
Non-Final Rejection mailed — §103
Aug 11, 2026
Response Filed
Oct 15, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
74%
Grant Probability
96%
With Interview (+22.6%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 540 resolved cases by this examiner. Grant probability derived from career allowance rate.

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