DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-4, 6 and 10-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yadav et al (Modified Widely Linear Filter for Simultaneous Multi-impairment Compensation) in view of Zhou et al (US Pub 20130138375).
Regarding claim 1. Yadav discloses an equalization signal processing circuit comprising:
a first filter configured to perform compensation for first distortion being included in a reception signal being acquired by coherent-receiving a signal being transmitted from a transmitter via a transmission path, with respect to the reception signal and a complex conjugate signal of the reception signal, and output the reception signal and the complex conjugate signal that are subjected to compensation for the first distortion (Fig 1(a), where an equalization circuit comprises a first filter (2x2 MIMO filter) configured to perform compensation for first distortion being included in a reception signal (e.g. Xin or Yin) acquired by coherent-receiving a signal being transmitted from a transmitter via a transmission path (as shown in Fig 1(b)), with respect to the reception signal (e.g. Xin or Yin) and a complex conjugate signal (e.g. from [ ]*) of the reception signal (e.g. Xin or Yin), and output the reception signal (e.g. Xin or Yin) and the complex conjugate signal (e.g. from [ ]*) that are subjected to compensation for the first distortion);
a filter group including a second filter configured to receive, as input signals, the reception signal and the complex conjugate signal that are subjected to compensation for the first distortion, perform compensation for second distortion being included in the reception signal, and output the reception signal being subjected to compensation for the second distortion (Fig 1(a), where the equalization circuit comprises a filter group (M-WL-CMA) that includes a second filter (e.g. FIR filter αx or FIR filter αy) configured to receive, as input signals, the reception signal (e.g. Xin or Yin) and the complex conjugate signal (e.g. from [ ]*) that are subjected to compensation for the first distortion, perform compensation for second distortion being included in the reception signal (e.g. Xin or Yin), and output the reception signal (e.g. Xin or Yin) being subjected to compensation for the second distortion); and
adaptively controlling a filter coefficient of the second filter, based on a difference between an output signal being output from the filter group and a predetermined value of the output signal (Fig 1(a), where the equalization circuit adaptively controls (e.g. via an error calculation) a filter tap/coefficient of the second filter (e.g. FIR filter αx or FIR filter αy) based on a difference between an output signal (e.g. Xout or Yout) output from the filter group (M-WL-CMA) and a predetermined value (e.g. Rx/y) of the output signal (e.g. Xout or Yout) (see equation (1))).
Yadav fails to explicitly disclose the equalization circuit comprises at least one memory storing instructions; and at least one processor configured to execute the instructions.
However, Zhou discloses
an equalization circuit comprises at least one memory storing instructions and at least one processor configured to execute the instructions (Fig 3, Fig 7, where an equalization circuit (330) comprises at least one memory storing instructions and at least one processor configured to execute the instructions (i.e. at computer 704)).
Therefore, it would have been obvious to one of ordinary skill in the art to combine the teachings of the equalization circuit as described in Yadav, with the teachings of the equalization circuit (330) as described in Zhou. The motivation being is that as shown an equalization circuit (330) comprises at least one memory and at least one processor and one of ordinary skill in the art can implement this concept into the equalization circuit as described in Yadav and better show and illustrate that the equalization circuit comprises at least one memory and at least one processor i.e. because the equalization circuit uses a memory and a processor in order to optimally perform calculations and computations and where such calculations and computations are used to optimally perform signal equalization and which combination is being made because the systems are similar and have overlapping components (e.g. equalization circuits,…) and which combination is a simple implementation of a known concept of a known equalization circuit (330) into another similar equalization circuit, namely, for its improvement and for optimization and which combination yields predictable results.
Regarding claim 3. Yadav as modified by Zhou also discloses the equalization signal processing circuit, wherein the second distortion includes in-receiver distortion occurring in a receiver, and the second filter compensates for in-receiver distortion (Yadav Fig 1(a), where the second distortion includes in-receiver distortion (e.g. phase noise) occurring in a receiver, and the second filter (e.g. FIR filter αx or FIR filter αy) compensates for in-receiver distortion (e.g. phase noise) (paras [2][3])).
Regarding claim 4. Yadav as modified by Zhou also discloses the equalization signal processing circuit, wherein the first filter includes a complex signal input complex coefficient filter having a predetermined tap length, and the second filter includes a multiple input single output (MISO) filter (Yadav Fig 1(a), where the first filter (2x2 MIMO filter) includes a complex signal input (i.e. due to real and imaginary parts) complex coefficient filter having a predetermined tap length (i.e. at 2x2 MIMO filter), and the second filter (e.g. FIR filter αx or FIR filter αy) includes a multiple input single output (MISO) filter).
Regarding claim 6. Yadav as modified by Zhou also discloses the equalization signal processing circuit, wherein the signal being transmitted from the transmitter is a polarization multiplexed signal, and the first filter and the second filter are arranged for each polarization (Yadav Fig 1(a), Fig 1(b), where the signal transmitted from the transmitter (as shown in Fig 1(b)) is a polarization multiplexed signal (i.e. due to X, Y polarizations), and the first filter (2x2 MIMO filter) and the second filter (e.g. FIR filter αx or FIR filter αy) are arranged for each polarization).
Regarding claim 10. Yadav as modified by Zhou also discloses a receiver comprising: a receiving circuit configured to coherent-receive a signal being transmitted from a transmitter via a transmission path; and the equalization signal processing circuit (Yadav Fig 1(a), Fig 1(b), where a receiving circuit (Receiver) is configured to coherent-receive a signal being transmitted from a transmitter via a transmission path (as shown in Fig 1(b)) and comprises the equalization circuit).
Regarding claim 11. Claim 11 is similar to claim 2, therefore, claim 11 is rejected for the same reasons as claim 2.
Regarding claim 12. Claim 12 is similar to claim 3, therefore, claim 12 is rejected for the same reasons as claim 3.
Regarding claim 13. Claim 13 is similar to claim 4, therefore, claim 13 is rejected for the same reasons as claim 4.
Regarding claim 14. Yadav as modified by Zhou also discloses a communication system comprising: a transmitter configured to transmit a signal via a transmission path; and the receiver (Yadav Fig 1(a), Fig 1(b), where a communication system comprises a transmitter configured to transmit a signal via a transmission path (as shown in Fig 1(b)) and comprises the receiver (Receiver)).
Regarding claim 15. Claim 15 is similar to claim 2, therefore, claim 15 is rejected for the same reasons as claim 2.
Regarding claim 16. Claim 16 is similar to claim 3, therefore, claim 16 is rejected for the same reasons as claim 3.
Regarding claim 17. Claim 17 is similar to claim 1, therefore, claim 17 is rejected for the same reasons as claim 1.
Regarding claim 18. Claim 18 is similar to claim 1, therefore, claim 18 is rejected for the same reasons as claim 1.
Claim 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yadav et al (Modified Widely Linear Filter for Simultaneous Multi-impairment Compensation) in view of Zhou et al (US Pub 20130138375) in further view of Venktasubramani et al (IQ Skew Tolerance Study of Modified Widely Linear Filter in 400 Gbps PM-16QAM System).
Regarding claim 7. Yadav as modified by Zhou also discloses the equalization signal processing circuit, and the at least one processor configured to execute the instructions to adaptively control the filter coefficient of the second filter by using an error back propagation method (Yadav Fig 1(a), where the equalization circuit adaptively controls the filter tap/coefficient of the second filter (e.g. FIR filter αx or FIR filter αy) by using an error back propagation method (i.e. as shown in Fig 1(a) and equation (1)).
Yadav as modified by Zhou fails to explicitly disclose the filter group includes one or more filters being connected in series along a signal path of the reception signal, on a downstream side with respect to the second filter.
However, Venktasubramani discloses
a filter group includes one or more filters being connected in series along a signal path of a reception signal, on a downstream side with respect to a second filter (Fig 1(a), where a filter group includes one or more filters (e.g. WL-DFE) connected in series along a signal path of a reception signal, on a downstream side with respect to a second filter (e.g. FIR filter αx or FIR filter αy)).
Therefore, it would have been obvious to one of ordinary skill in the art to modify the second filter (e.g. FIR filter αx or FIR filter αy) as described in Yadav as modified by Zhou, with the teachings of the second filter (e.g. FIR filter αx or FIR filter αy) as described in Venktasubramani. The motivation being is that as shown one or more filters (e.g. WL-DFE) can be on a downstream side of a second filter (e.g. FIR filter αx or FIR filter αy) and one of ordinary skill in the art can implement this concept into the second filter (e.g. FIR filter αx or FIR filter αy) as described in Yadav as modified by Zhou and have one or more filters (e.g. WL-DFE) be on a downstream side of the second filter (e.g. FIR filter αx or FIR filter αy) i.e. as an alternative so as to have the second filter (e.g. FIR filter αx or FIR filter αy) with a known technique of a known second filter (e.g. FIR filter αx or FIR filter αy) for the purpose of optimally adding an additional filter (e.g. WL-DFE) in order to compensate for transmitter imbalance and which modification is being made because the systems are similar and have overlapping components (e.g. FIR filters αx and FIR filters αy) and which modification is a simple implementation of a known concept of a known second filter (e.g. FIR filter αx or FIR filter αy) into another similar second filter (e.g. FIR filter αx or FIR filter αy), namely, for its improvement and for optimization and which modification yields predictable results.
Allowable Subject Matter
Claims 2, 5, and 8-9 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The additional prior art considered to the Applicant’s disclosure and not relied upon is the following.
Nakamura et al (US Pub 20240267129) and more specially Fig 3.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIBSON J SANCHEZ whose telephone number is (571)272-0868. The examiner can normally be reached on Mon-Fri 10:00-6:00.
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/DIBSON J SANCHEZ/
Primary Examiner, Art Unit 2636
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