Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1.
b. Claims 1-10 are pending on the application.
Preliminary Amendment
2. Acknowledgment is made of applicant’s Preliminary Amendment, filed 08/05/2024. The changes and remarks disclosed therein were considered.
Claims 1-10 are pending in the application.
Drawings
3. The drawings were received on 08/05/2024. These drawings are review and accepted by examiner.
Priority
4. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
5. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 08/05/2024. The information disclosed therein was considered.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1 and 3-5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Asao (Pub. No.: US 2010/0238718 A1).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding to independent claim 1, Asao in Figures 1-11 are directly discloses a magnetoresistive effect memory (a mram circuit as show in Figures 1-11) comprising:
a magnetoresistive element (a MTJ 22, Fig. 6) including a fixed layer (a fixed layer 22A) whose magnetization direction is fixed and a recording layer (a recording layer 22C) whose magnetization direction changes (the MTJ 22 by the spin transfer method by which a write current is supplied to the MTJ element 22, Fig. 6); and
a write circuit (a select transistor 13, Fig. 6) that reverses magnetization of the recording layer so that a resistance value of the magnetoresistive element (the select transistor 13) is switched between a low resistance value (the MTJ 22 set parallel state (low-resistance state) as binary 0) and a high resistance value (the MTJ 22 set antiparallel (high-resistance state) as binary 1)(the select transistor 13 coupled to the MTJ 22, Fig. 6), wherein
the magnetization of the recording layer (the recording layer 22C) rotates by precession around a magnetic field (a nonmagnetic layer 22B) in a plane direction of the layer when a voltage (a gate of transistor 13) is applied to the magnetoresistive element (the gate of the select transistor 13 apply the voltage to the MTJ element 22, Fig. 6),
the resistance value of the magnetoresistive element gradually changes between the low resistance value (the low-resistance as binary 0)(the MTJ 22 set parallel state (low-resistance state) in which the magnetization direction in the fixed layer 22A and recording layer 22C are parallel, the resistance of the MTJ element 22 is minimum and the state is defined as binary 0) and the high resistance value (the high-resistance as binary 1) during the rotation of the magnetization of the recording layer (the MTJ 22 set antiparallel (high-resistance state) in which magnetization direction in the fixed layer 22A and recording 22C are antiparallel, the resistance of the MTJ element 22 is maximum and the state is defined as binary 1, column 3, paragraph 0043), and
the write circuit (the select transistor 13) reverses the magnetization of the recording layer so that the resistance value of the magnetoresistive element is switched from the high resistance value (the high-resistance as binary 1) to the low resistance value (the low-resistance as binary 0) by applying a current limited (a current IAP->P and IP->AP) so as to have a predetermined magnitude to the magnetoresistive element (for example, the current force of the select transistor 13 defines the write current to be supplied to the MTJ element 22. The MTJ 22 function as a resistance element, see at least in Figures 1-3 and 6, column 1, paragraph 0027 to column 4, paragraph 0057 and the related disclosures).
Regarding dependent claim 3, Asao in Figures 1-11 are directly discloses a magnetoresistive effect memory (a mram circuit as show in Figures 1-11) wherein the limited current is a constant current (a current (IAP->P and IP->AP) of the select transistor 13 applied two different current to the MTJ 22 such as current constant current).
Regarding dependent claim 4, Asao in Figures 1-11 are directly discloses a magnetoresistive effect memory (a mram circuit as show in Figures 1-11) wherein the write circuit (the select transistor 13) applies a current limited (a current IAP->P and IP->AP) in stages so as to have different predetermined magnitudes to the magnetoresistive element during a reversal of the magnetization of the recording layer (the recording layer 22C)(a current (IAP->P and IP->AP) of the select transistor 13 applied two different current to the MTJ 22) so.
Regarding dependent claim 5, Asao in Figures 1-11 are directly discloses a magnetoresistive effect memory (a mram circuit as show in Figures 1-11) wherein the write circuit (the select transistor 13) reverses the magnetization of the recording layer so that the resistance value of the magnetoresistive element is switched from the low resistance (the low-resistance as binary 0) value to the high resistance (the high-resistance as binary 1) value by applying a constant voltage to the magnetoresistive element (the gate of select transistor 13 applied apply the voltage to the MTJ 22 such as constant volatge).
Allowable Subject Matter
7. Claims 2 and 6-10, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claim 2, the prior art fails to tech or suggest the claimed limitations, namely, the write circuit applies the limited current having a pulse width longer than a magnetization reversal period of the recording layer to the magnetoresistive element.
With respected to dependent claim 6, the prior art fails to tech or suggest the claimed limitations, namely, the write circuit applies the constant voltage having a pulse width that is the same as a magnetization reversal period of the recording layer to the magnetoresistive element.
With respected to dependent claims 7-8, the prior art fails to tech or suggest the claimed limitations, namely, a read circuit that detects the resistance value of the magnetoresistive element by applying a voltage at which the magnetization of the recording layer is not reversed to the magnetoresistive element, wherein the write circuit reverses the magnetization of the recording layer so that the resistance value of the magnetoresistive element is switched from the high resistance value to the low resistance value by applying the limited current to the magnetoresistive element whose resistance value is detected to be the high resistance value by the read circuit.
With respected to dependent claim 9, the prior art fails to tech or suggest the claimed limitations, namely, the write circuit initializes the resistance value of the magnetoresistive element to the low resistance value by applying the limited current to the magnetoresistive element, and reverses the magnetization of the recording layer so that the resistance value of the magnetoresistive element is switched from the low resistance value to the high resistance value by applying a constant voltage to the magnetoresistive element after initialization.
With respected to dependent claim 10, the prior art fails to tech or suggest the claimed limitations, namely, a read circuit that detects the resistance value of the magnetoresistive element by applying a low voltage at which the magnetization of the recording layer is not reversed to the magnetoresistive element in order to determine whether or not switching of the resistance value of the magnetoresistive element by the write circuit is successful.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Victora et al (US. 8,134,864 B2) discloses exchange assisted spin transfer torque switch in mram.
Kajiyama (US. 2008/0089118 A1) discloses magnetic random access memory and method of manufacturing the same.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
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/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov