DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-12, and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fujii et al. (PCT Pub. No. WO2020/262584A1 using corresponding U.S. Pub. No. 20220367558 for citations).
Regarding claim 1, Fujii discloses:
A solid-state imaging device (main part of the pixel unit of the solid-state imaging apparatus, par. 134) comprising:
a photoelectric conversion region (each sensor pixel 12 includes, for example, a photodiode PD (example of a photoelectric conversion element) where the photodiode PD performs photoelectric conversion to generate charge corresponding to the amount of light received, par. 129 and Figs. 4 and 53) formed in a semiconductor substrate (first substrate portion 10 includes the semiconductor layer 701 that is used as a first semiconductor layer, where semiconductor layer 701 includes a plurality of island regions 703 arranged adjacent to one another via an element isolation region 702 in a planar form, and one island region 703 corresponds to one sensor pixel 12, par. 136, 281, 282, and Figs. 4 and 53), the semiconductor substrate having a first surface and a second surface with different heights formed adjacent to a wiring layer (light receiving side of first substrate 100 and wiring layer 100T-side surface of first substrate 100 next to wiring layer 100T, par. 281-282 and Fig. 53);
a floating diffusion region formed on an opposite side of the semiconductor substrate from the photoelectric conversion region relative to the first surface and between the first surface and the second surface (floating diffusion FD formed on an opposite side of first substrate 100 from the photodiode PD and between the light receiving side of first substrate 100 and wiring layer 100T side of first substrate 100, where floating diffusion FD includes an n-type contact region 705, par. 129, 281, 282, and Fig. 53); and
a transfer transistor that transfers charges generated in the photoelectric conversion region to the floating diffusion region (transfer transistor TR, where in an on-state, the transfer transistor TR transfers charge in the photodiode PD to the floating diffusion FD, par. 132, 281, 282, and Figs. 4 and 53), wherein
the transfer transistor has a vertical gate electrode structure in which a gate electrode is formed on a side surface connecting the first surface and the second surface (gate electrode 710 of the transfer transistor TR, for example, extends from a front surface of the semiconductor layer 701 through a well region 704 to a depth where the gate electrode 710 reaches the photodiode PD, par. 132, 281, 282, and Fig. 4 and 53).
Regarding claim 2, Fujii further discloses:
gate electrode of the transfer transistor is further formed on the second surface (gate electrode 710 is formed on the well region 704 of substrate 100, Fig. 4).
Regarding claim 3, Fujii further discloses:
floating diffusion region is shared by a plurality of pixels (four adjacent sensor pixels 12 may share one floating diffusion contact, par. 512).
Regarding claim 5, Fujii further discloses:
gate electrode formed on the side surface has a height of 0.2 μm or more (gate electrode 710 is over double the thickness of conductive pad 842 and polycrystal silicon film, with a film thickness of approximately 100 nm, formed all over the surface of the titanium oxide film that is formed over the surface of semiconductor layer 701, par. 188 and Fig. 20).
Regarding claim 6, Fujii further discloses:
amplification transistor, a reset transistor, and a selection transistor also each include a pixel transistor having the vertical gate electrode structure (gate electrode 806a of the amplifying transistor AMP, gate electrode 806b provided on the gate insulating film 805 of reset transistor RST, and gate electrode of select transistor SEL formed in second substrate 200 have a vertical structure, par. 149, 363, 364, and Figs. 4, 53, and 62).
Regarding claim 7, Fujii further discloses:
gate electrode has a recessed planar shape surrounding the floating diffusion region with three surfaces (gate electrode 710 has is recessed though the well region and has multiple surfaces surrounding the surfaces of floating diffusion FD region 705, Figs. 4 and 53).
Regarding claim 8, Fujii further discloses:
a pixel trench portion obtained by cutting into the semiconductor substrate to a predetermined depth from a back surface that is an opposite side of the semiconductor substrate from the first surface and the second surface, the pixel trench portion partitioning the photoelectric conversion region into pixel units (photodiode PD is located in areas/cutouts of substrate 100 toward a back surface side, par. 136, 281, 282, and Figs. 4 and 53).
Regarding claim 9, Fujii further discloses:
a pixel trench portion extending through the semiconductor substrate and partitioning the photoelectric conversion region into pixel units (element isolation region 702 electrically isolates the island regions 703 adjacent to each other and the element isolation region 702 has, for example, an STI (Shallow Trench Isolation) structure and extends from the major surface of the semiconductor layer 701 in a depth direction, par. 138).
Regarding claim 10, Fujii further discloses:
a doped polysilicon layer connecting the floating diffusion region of each pixel partitioned by the pixel trench portion (pad portion 120 is intended to connect the floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) in the respective pixels 541A, 541B, 541C, and 541D to one another, where the pad portion 120 is disposed in each pixel sharing unit 539 at the central portion of the pixel sharing unit 539 in plan view (FIG. 54B), where pad portion 120 includes polysilicon (Poly Si), more specifically, doped polysilicon with impurities addition, par. 293, 300, and Figs. 54B).
Regarding claim 11, Fujii further discloses:
an amplification transistor, a reset transistor, and a selection transistor each include a pixel transistor having a planar gate electrode (gate electrode 806a of the amplifying transistor AMP, gate electrode 806b provided on the gate insulating film 805 of reset transistor RST, and gate electrode of select transistor SEL formed in second substrate 200 have a three dimensional structure, par. 149, 363, 364, and Figs. 4, 53, and 62).
Regarding claim 12, Fujii further discloses:
a step is formed between the first surface and the second surface by subjecting, to etching, a region of the second surface of the semiconductor substrate other than at least a region where the floating diffusion region is formed (element isolation regions 702 are formed on the major surface side of the semiconductor layer 701, and island regions 703 that are used as element formation regions enclosed and delimited by the element isolation regions 702 are formed and element isolation regions 702 are formed by using a photolithography technology and an anisotropic dry etching technology, which are well known, to form separation grooves extending from the major surface of the semiconductor layer 701 in the depth direction and then selectively embedding an insulating film into the separation grooves, where the insulating film is embedded into the separation grooves by forming, by a CVD method, a silicon oxide film all over the major surface of the semiconductor layer 701 including the inside of the separation grooves, where floating diffusion FD is formed in semiconductor layer 701, par. 154 and Fig. 5).
Regarding claim 14, see the rejection of claim 1 and note that the limitations of claim 14 were shown and that the solid state apparatus is in an imaging system such as a camera as seen in par. 391.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujii et al. (PCT Pub. No. WO2020/262584A1 using corresponding U.S. Pub. No. 20220367558 for citations).
Regarding claim 4, Fujii further discloses:
photoelectric conversion region is formed for each pixel (each sensor pixel 12 includes, for example, a photodiode PD (example of a photoelectric conversion element) where the photodiode PD performs photoelectric conversion to generate charge corresponding to the amount of light received, par. 129 and Figs. 4 and 53).
Fujii is silent with regards to one on-chip lens is arranged for a plurality of pixels, and each pixel sharing the one on-chip lens is configured to be able to output a phase difference signal. Official Notice is taken that it was well known before the effective filing date of the claimed invention to include using a single on-chip microlens for multiple pixels in order to output a phase detection signal. This is advantageous in that phase detection autofocusing can be performed using an image sensor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include one on-chip lens is arranged for a plurality of pixels, and each pixel sharing the one on-chip lens is configured to be able to output a phase difference signal.
Regarding claim 13, Fujii further discloses:
a step is formed between the first surface and the second surface including at least a region where the floating diffusion region is formed (element isolation regions 702 are formed on the major surface side of the semiconductor layer 701, and island regions 703 that are used as element formation regions enclosed and delimited by the element isolation regions 702 are formed, where floating diffusion FD is formed in semiconductor layer 701, par. 154 and Fig. 5).
Note that Fujii discloses using epitaxial growth to form components as seen in par. 192. Fujii is silent with regards to by subjecting, to selective epitaxial growth, a region of the first surface of the semiconductor substrate. Official Notice is taken that it was well known before the effective filing date of the claimed invention to include using epitaxial growth to form different components on/in semiconductors substrates including a floating diffusion. This is advantageous in that precise doping levels can be achieved. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include by subjecting, to selective epitaxial growth, a region of the first surface of the semiconductor substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS G GILES whose telephone number is (571)272-2824. The examiner can normally be reached M-F 6:45AM-3:15PM EST (HOTELING).
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/NICHOLAS G GILES/ Primary Examiner, Art Unit 2639