Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 8-15 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-15 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding Claims 8 and 15, the limitation “returning the register number usable by the CPU resulting from the translation to the register number as an original register number” renders the claims indefinite.
Each of Claims 8 and 15 previously recites two distinct translating steps “translating a stored address … into a different stored address” and “translating a register number of a general-purpose register … into a register number usable by the CPU” so the phrase “the translation” is ambiguous as to which of the two translations is referenced. Additionally, each claim previously introduces two distinct register numbers (“a register number of a general-purpose register” and “a register number usable by the CPU”), rendering “the register number” as the target of the return ambiguous. As a result, one of ordinary skill cannot determine the scope of the claim with reasonable certainty.
Regarding Claim 10, the limitation “translating a stored address stored in the memory allocated per data in a data region” renders the claim indefinite.
Claim 8, from which Claim 10 depends, recites three distinct memory referents: “a memory” of the update software generation device, “a memory” of the CPU, and “a memory on the CPU” in which the stored address resides. Because Claim 10 refers only to “the memory” without specifying which one, the antecedent is ambiguous and the scope of the claim cannot be ascertained with reasonable certainty.
Regarding Claim 12, the limitation “returning an operand address or immediate data resulting from the translation to the operand address or the immediate data as an original operand address or original immediate data” renders the claim indefinite.
Claim 12 depends from Claim 8, which already recites two distinct translating steps, and Claim 12 itself adds a third (“translating an operand address or immediate data”). The bare phrase “the translation” in the return step is therefore ambiguous as to which of the three translations is referenced. In addition, the use of the indefinite article in “returning an operand address or immediate data” introduces a new operand address rather than referring back to the previously translated operand address, further obscuring the scope of the claim.
Regarding Claim 13, the limitation “translating a value of each piece of data in the data region defined at least by the constant and the structure in the update software” renders the claim indefinite.
Claim 13 depends from Claim 8, which does not introduce “a data region,” “a constant,” or “a structure”; those terms are first introduced in Claim 10. Accordingly, each of “the data region,” “the constant,” and “the structure” in Claim 13 lacks proper antecedent basis, leaving one of ordinary skill in the art unable to ascertain the scope of the claim with reasonable certainty.
Regarding Claim 13, the limitation “returning data resulting from the translation to the data as original data” further renders the claim indefinite.
Claim 13 introduces an additional translating step (“translating a value of each piece of data”) on top of the two translating steps already recited in Claim 8, so the phrase “the translation” in the return step is ambiguous as to which of the three translations is referenced.
Dependent claims 9, 11 and 14 are also rejected under 35 U.S.C. 112(b) as being indefinite for failing to cure the deficiencies of their independent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8–10, 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Vauclair (US 2010/0332759 A1) in view of de Jong (US 2005/0071655 A1).
Regarding Claim 8, Vauclair teaches
A software update system comprising an update software generation device and a central processing unit (CPU), the update software generation device generating update software to update software running on the CPU, the CPU updating the software using the update software generated by the update software generation device (Para 0032, Program conversion may be performed by a program conversion apparatus, such as a computer that is programmed to perform program conversion) Examiner Comments: Vauclair’s program conversion apparatus, embodied as a computer that converts a program, corresponds to the claimed update software generation device, and Vauclair’s separate processing device that executes the converted program corresponds to the claimed CPU.
wherein the update software generation device comprises a processor to execute a program and a memory to store the program which, when executed by the processor, performs the recited process (Para 0032, Program conversion may be performed by a program conversion apparatus, such as a computer that is programmed to perform program conversion) Examiner Comments: a computer programmed to perform program conversion inherently comprises a processor that executes a stored program and a memory that stores that program.
translating a stored address stored in a memory on the CPU allocated per at least one instruction code of an assembler code or a machine language code of the update software into a different stored address from a normal stored address (Para 0006, a sequence of original instruction addresses within the original address space is mapped to a limited set of ranges of target addresses for addressing reordered instructions) Examiner Comments: mapping each original instruction address to a target address drawn from a different range reads on translating a stored address allocated per instruction code into a different stored address from the normal stored address.
wherein the CPU comprises a processor to execute a program and a memory to store the program which, when executed by the processor, performs the recited process (Para 0008, A processing device … is provided for executing the converted program. This processing device addresses successive instructions in correspondence with the rearranged addresses) Examiner Comments: Vauclair’s processing device that executes the converted program is a CPU having a processor and a memory storing the program it executes.
returning the different stored address resulting from the translation to the normal stored address (Para 0031, the data processing device comprises software and/or hardware to preprocess the program before execution. Preprocessing is performed so that the rearrangement of the sequence of instructions is undone) Examiner Comments: undoing the rearrangement of the instruction sequence during on-device preprocessing restores each translated address to its original normal address.
Vauclair did not specifically teach
the program stored in the memory of the update software generation device further performs, when executed by the processor, a process of translating a register number of a general-purpose register for use in an instruction code of an assembler code or a machine language code of the update software into a register number usable by the CPU, and returning the register number usable by the CPU resulting from the translation to the register number as an original register number
the translation into the register number usable by the CPU is performed before or after the translation into the different stored address, and the register number usable by the CPU is returned to the original register number before or after the return to the normal stored address.
However, de Jong (US 2005/0071655 A1) teaches
the program stored in the memory of the update software generation device further performs, when executed by the processor, a process of translating a register number of a general-purpose register for use in an instruction code of an assembler code or a machine language code of the update software into a register number usable by the CPU (Para 0012, transforming the application program code into transformed application program code that uses one of multiple opcode value encoding schemes of a dispatch table associated with the application program) Examiner Comments: de Jong’s technique of re-encoding an instruction-encoded field under one of multiple dispatch-table schemes is the same technique recited for the register-number field, so applying it to the register number of a general-purpose register yields translating that register number into a register number usable by the CPU.
returning the register number usable by the CPU resulting from the translation to the register number as an original register number (Para 0084, User device 305 includes a deobfuscator 320 configured to deobfuscate obfuscated code stored on the user device 305) Examiner Comments: de Jong’s on-device deobfuscator that decodes the re-encoded instruction field back to its executable form teaches returning the CPU-usable register number to the original register number.
the translation into the register number usable by the CPU is performed before or after the translation into the different stored address, and the register number usable by the CPU is returned to the original register number before or after the return to the normal stored address Examiner Comments: because the address translation and the register-number translation are independent, reversible operations, performing one before or after the other presents only a finite number of identified, predictable orderings, rendering the recited ordering an obvious design choice.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the register-number translation of de Jong with the address-rearrangement system of Vauclair in order to add a second, independently reversible layer of obfuscation that further conceals the operation of the update software while it is in transit and that is undone on the executing device without requiring added decryption resources, which is no more than the use of a known obfuscation technique to improve a similar obfuscation system in the same way, yielding the predictable result of stronger protection against theft and reverse engineering (de Jong [Summary]).
Regarding Claim 9, Vauclair and de Jong teach
The software update system of Claim 8.
de Jong teaches
wherein the update software generation device translates a register number of a floating point register for use in an instruction code into a register number usable by the CPU, and the CPU returns the register number to the original register number (Para 0012, transforming the application program code into transformed application program code that uses one of multiple opcode value encoding schemes of a dispatch table associated with the application program) Examiner Comments: a floating point register is merely another register field of an instruction code, so de Jong’s field re-encoding technique applies to it in the same manner as to a general-purpose register.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the register-number translation of de Jong with the address-rearrangement system of Vauclair in order to add a second, independently reversible layer of obfuscation that further conceals the operation of the update software while it is in transit and that is undone on the executing device without requiring added decryption resources, which is no more than the use of a known obfuscation technique to improve a similar obfuscation system in the same way, yielding the predictable result of stronger protection against theft and reverse engineering (de Jong [Summary]).
Regarding Claim 10, Vauclair and de Jong teach
The software update system of Claim 8.
Vauclair teaches
wherein the update software generation device translates a stored address stored in the memory allocated per data in a data region defined at least by a constant and a structure in the update software into a different stored address from a normal stored address (Para 0006, a sequence of original instruction addresses within the original address space is mapped to a limited set of ranges of target addresses for addressing reordered instructions) Examiner Comments: a stored address allocated per data in a data region is the same kind of address that Vauclair maps from an original range to a different target range, and extending that mapping to the data region is the application of a known technique to obtain the predictable result of also concealing the data layout.
Regarding Claim 12, Vauclair and de Jong teach
The software update system of Claim 8.
de Jong teaches
wherein the update software generation device translates an operand address or immediate data for use in an instruction code of an assembler code or a machine language code of the update software, and the CPU returns the operand address or immediate data to an original operand address or original immediate data (Para 0056, application program instructions interleaved with application program data in an instruction stream) Examiner Comments: because de Jong encodes an instruction stream in which program data such as operands and immediate values is interleaved with instructions and decodes it on the device, the operand address or immediate data is translated on the generation side and returned to its original value on the CPU side.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the register-number translation of de Jong with the address-rearrangement system of Vauclair in order to add a second, independently reversible layer of obfuscation that further conceals the operation of the update software while it is in transit and that is undone on the executing device without requiring added decryption resources, which is no more than the use of a known obfuscation technique to improve a similar obfuscation system in the same way, yielding the predictable result of stronger protection against theft and reverse engineering (de Jong [Summary]).
Regarding Claim 15, Vauclair and de Jong teach
Claim 15 recites a software update method comprising steps corresponding to the functions performed by the software update system of Claim 8, and is rejected under 35 U.S.C. 103 for the same reasons as Claim 8.
Claims 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Vauclair (US 2010/0332759 A1) in view of de Jong (US 2005/0071655 A1) further in view of Collberg (US 6,668,325 B1).
Regarding Claim 11, Vauclair and de Jong teach
The software update system of Claim 8.
Vauclair and de Jong did not specifically teach
generating an instruction code or a data string of an assembler code or a machine language code of the update software as a pseudo-code, inserting the generated pseudo-code into an unused or no-longer-used stored address, and removing the inserted pseudo-code by the CPU.
However, Collberg (US 6,668,325 B1) teaches
generating an instruction code or a data string of an assembler code or a machine language code of the update software as a pseudo-code and inserting the generated pseudo-code, the unused or no-longer-used stored addresses being those vacated by the address rearrangement of Vauclair (Col 15, ln 25-43, Computation transformations can insert new (redundant or dead) code, or make algorithmic changes to the source application) Examiner Comments: Collberg’s insertion of new redundant or dead code into the application teaches generating an instruction code or data string as a pseudo-code and inserting it, and Vauclair’s remapping vacates the original addresses into which such pseudo-code may be inserted.
the CPU removing the inserted pseudo-code (Col 3, ln 1-20, a deobfuscating tool adopted to remove obfuscations from an obfuscated application by use of slicing, partial evaluation, dataflow analysis, or statistical analysis) Examiner Comments: Collberg’s deobfuscating tool that removes the inserted obfuscations teaches the CPU removing the inserted pseudo-code.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add Collberg’s dead-code insertion and removal to the Vauclair and de Jong system in order to further obscure the number and boundaries of functions in the update software and thereby increase resistance to reverse engineering, which is the predictable use of a known obfuscation transform combined with the known address-rearrangement and field re-encoding transforms (Collberg [abstract/summary]).
Regarding Claim 13, Vauclair and de Jong teach
The software update system of Claim 8.
Vauclair and de Jong did not specifically teach
translating a value of each piece of data in the data region defined at least by the constant and the structure in the update software, and the CPU returning the translated data to the original data.
However, Collberg (US 6,668,325 B1) teaches
translating a value of each piece of data in the data region defined at least by the constant and the structure in the update software (Col 6, ln 63-67, An array can be split into several subarrays, two or more arrays can be merged into a single array) Examiner Comments: Collberg’s data transformations that restructure the values held in arrays and other data structures teach translating the value of each piece of data in the data region defined by a constant and a structure.
the CPU returning the data resulting from the translation to the original data (Col 3, ln 15-21, a deobfuscating tool adopted to remove obfuscations from an obfuscated application by use of slicing, partial evaluation, dataflow analysis, or statistical analysis) Examiner Comments: Collberg’s deobfuscating tool that removes the data obfuscations restores the translated data to its original values.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add Collberg’s dead-code insertion and removal to the Vauclair and de Jong system in order to further obscure the number and boundaries of functions in the update software and thereby increase resistance to reverse engineering, which is the predictable use of a known obfuscation transform combined with the known address-rearrangement and field re-encoding transforms (Collberg [abstract/summary]).
Claims 14 are rejected under 35 U.S.C. 103 as being unpatentable over Vauclair (US 2010/0332759 A1) in view of de Jong (US 2005/0071655 A1) further in view of Chiang (US 2006/0206537 A1).
Regarding Claim 14, Vauclair and de Jong teach
The software update system of Claim 8.
Vauclair and de Jong did not specifically teach
storing a current processing and determining a new processing, generating difference update software that partially updates only a difference between the stored current processing and the determined new processing, merging the difference update software, and the CPU removing the merged difference update software to return to the original update software.
However, Chiang (US 2006/0206537 A1) teaches
storing a current processing, determining a new processing, and generating difference update software that partially updates only a difference between the stored current processing and the determined new processing (Para 0029, The file differencing algorithm 114 receives the new file 112, compares it to the original file 110, and calculates the byte-level differences between the compared files) Examiner Comments: Chiang’s storage of an original (old) version and determination of a new version, followed by computing the byte-level differences to produce a delta file, teaches storing current processing, determining new processing, and generating difference update software that partially updates only the difference.
merging the difference update software, and the CPU removing the merged difference update software to return to the original update software (Para 0050, The file updating algorithm of the client device then generates a copy of the new file or EBSC) Examiner Comments: Chiang’s client-device file updating algorithm that reconstructs the complete new file from the delta and the original teaches the CPU removing the merged difference update software to return to the original update software.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Chiang’s difference (delta) update into the Vauclair and de Jong system in order to transmit only the changed portion of the update software and thereby reduce transmission bandwidth and storage on resource-limited embedded devices, which is a predictable and well-recognized benefit of delta updating (Chaing [abstract/Summary]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMIR SOLTANZADEH whose telephone number is (571)272-3451. The examiner can normally be reached M-F, 9am - 5pm ET.
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/AMIR SOLTANZADEH/Examiner, Art Unit 2191
/WEI Y MUI/Supervisory Patent Examiner, Art Unit 2191
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