Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-24 and 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moss (US 20150070850 A1), in view of Martinez (US 9867285 B2).
Regarding independent claim 21, Moss teaches a stacked power converter assembly ([0017], "FIG. 1 illustrates an example embodiment of a three-dimensional half-bridge power converter module…"), comprising: an interposer (Fig. 2, 290; [0030], "...the power converter sub-assembly components are configured for direct mounting of the power converter components to a PCBA 290…"); one or more integrated circuits arranged on top of the interposer (Fig. 2, 250; [0031], "...define a cavity 240, within which is mounted driver IC 250."); one or more passive electrical components stacked on top of the one or more integrated circuits (Fig. 2, 230; [0031], "A load inductor component 230 is stack attached to power block 210 and interconnect spacer block 220…"); and wherein the one or more integrated circuits and the one or more passive electrical components are configured to perform a power conversion of an input voltage and/or current to an output voltage and/or current ([0010], "The Disclosure describes apparatus and methods adaptable for power conversion…", [0011], "...an underside drain with a VIN input...and an underside VOUT output.").
However, Moss does not teach one or more current-carrying metal strips arranged and connected between the one or more passive electrical components and the interposer.
However, in the same field of endeavor, Martinez teaches one or more current-carrying metal strips arranged and connected between the one or more passive electrical components and the interposer (Fig. 5, 44; (Col. 5, Lines 48-51), "Instead of being mounted directly to printed contact pads 22 on substrate 12, SMT component 38 may be mounted to an intervening conductive standoff 44, sometimes referred to as a conductive structure or metal member.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked power converter of Moss with the metal strips of Martinez so as "to electrically connect surface mount technology components to the printed circuit board contacts", (Martinez, Col. 1, Lines 52-53).
Regarding dependent claim 22, Moss, as previously modified by Martinez, teaches the stacked power converter assembly according to claim 21, and further teaches wherein the one or more passive electrical components are surface-mount device (SMD) components ([0029], "Module interconnect substrate carrier 190 can include any suitable structure that provides a module interconnect surface, and means to mount power converter module 100 to a PCBA, including providing appropriate interconnect.").
Regarding dependent claim 23, Moss, as previously modified by Martinez, teaches the stacked power converter assembly according to claim 21, and further teaches wherein the one or more passive electrical components comprise a chip inductor and/or a chip capacitor and/or a ceramic capacitor (Fig. 2, 230; [0031], "A load inductor component 230 is stack attached to power block 210 and interconnect spacer block 220…").
Regarding dependent claim 24, Moss, as previously modified by Martinez, teaches the stacked power converter assembly according to claim 21, and further teaches wherein the interposer is a printed circuit board, a lead-frame substrate, or a silicon substrate (Fig. 2, 290; [0030], "...the power converter sub-assembly components are configured for direct mounting of the power converter components to a PCBA 290…").
Regarding dependent claim 36, Moss, as previously modified by Martinez, teaches the stacked power converter assembly according to claim 21. However, as previously combined, they do not teach wherein the stacked power converter assembly has a maximum surface of 20 mm^2.
However, Martinez further teaches wherein the stacked power converter assembly has a maximum surface of 20 mm^2 (Fig. 5, 38; (Col. 5, Lines 27-28), "In these embodiments, SMT component 38 may have a length of 0.6 mm and a width of 0.3 mm.", (In this case, the surface area is 0.18 mm^2, which is much less than the maximum surface area given in the present application)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked power converter assembly as described by the combination of Moss and Martinez with the surface area of the device of Martinez so as to "be housed within [a] housing", (Martinez, Col. 5, Line 25).
Claim(s) 25, 26, and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moss (US 20150070850 A1), in view of Martinez (US 9867285 B2) and Tsai (US 20200411444 A1).
Regarding dependent claim 25, Moss, as previously modified by Martinez, teaches the stacked power converter assembly according to claim 21. However, as previously combined, they do not teach wherein the one or more current-carrying metal strips have one or more substantially flat bottom surfaces.
However, in the same field of endeavor, Tsai teaches wherein the one or more current-carrying metal strips have one or more substantially flat bottom surfaces (Fig. 2D, 230, (The bottom is flat)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked power converter assembly as described by the combination of Moss and Martinez with the flat bottoms of Tsai so that "the conductive elements may be used to hold or receive conductive pillars", (Tsai, [0020]).
Regarding dependent claim 26, Moss, as previously modified by Martinez, teaches the stacked power converter assembly according to claim 21. However, as previously combined, they do not teach wherein the one or more current-carrying metal strips carry the one or more passive electrical components.
However, in the same field of endeavor, Tsai teaches wherein the one or more current-carrying metal strips carry the one or more passive electrical components (Fig. 2D, 230, 226; [0065], "...each of the conductive features 230 includes a support element 226 and a solder element 228…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked power converter assembly as described by the combination of Moss and Martinez with the carrying metal strips so that "the warpage of the interposer substrate is significantly reduced…[and] the reliability and performance of the package structure are therefore improved", (Tsai, [0074]).
Regarding dependent claim 34, Moss, as previously modified by Martinez, teaches the stacked power converter assembly according to claim 21. However, as previously combined, they do not teach further comprising a molding material encapsulating the one or more integrated circuits and/or the one or more current-carrying metal strips.
However, in the same field of endeavor, Tsai teaches further comprising a molding material encapsulating the one or more integrated circuits and/or the one or more current-carrying metal strips (Fig. 2D, 240; [0071], "As shown in FIG. 2D, a protective layer 240 is formed to surround the conductive features 230 and the semiconductor die 122, in accordance with some embodiments.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked power converter assembly as described by the combination of Moss and Martinez with the molding material of Tsai so that "warpage and/or voids are prevented or reduced", (Tsai, [0096]).
Claim(s) 27 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moss (US 20150070850 A1), in view of Martinez (US 9867285 B2), Tsai (US 20200411444 A1), and Bhagavat (US 20200312766 A1).
Regarding dependent claim 27, Moss, as previously modified by Martinez and Tsai, teaches the stacked power converter assembly according to claim 26. However, as previously combined, they do not teach wherein the one or more current-carrying metal strips are configured to carry high electrical current of the stacked power converter assembly.
However, in the same field of endeavor, Bhagavat teaches wherein the one or more current-carrying metal strips are configured to carry high electrical current of the stacked power converter assembly (Fig. 2, 205a-e; [0056], "The molding layer 120 includes plural conductive pillars, a few of which are labeled 205a, 205b, 205c, 205d and 205e…", [0002], "For example, an integrated circuit operating at 100 watts and 1 volt may draw nearly 100 amps of current.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked power converter assembly as described by the combination of Moss, Martinez, and Tsai with the high current of Bhagavat so as to not "have current limitations", (Bhagavat, [0021]).
Regarding dependent claim 28, Moss, as previously modified by Martinez, Tsai, and Bhagavat, teaches the stacked power converter assembly according to claim 27, and Bhagavat further teaches wherein the high electrical current of the stacked power converter assembly is at least 10 mA ([0002], "For example, an integrated circuit operating at 100 watts and 1 volt may draw nearly 100 amps of current.").
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moss (US 20150070850 A1), in view of Martinez (US 9867285 B2), Tsai (US 20200411444 A1), and Nishizawa (US 20170271280 A1).
Regarding dependent claim 29, Moss, as previously modified by Martinez and Tsai, teaches the stacked power converter assembly according to claim 26. However, as previously combined, they do not teach wherein each of the one or more current-carrying metal strips has an upper surface of at least 0.1 mm^2.
However, in the same field of endeavor, Nishizawa teaches wherein each of the one or more current-carrying metal strips has an upper surface of at least 0.1 mm^2 (Fig. 3, 131, 132, 133; [0043], "Moreover, the diameter of the conductive posts 131, 132, and 133 is greater than or equal to approximately 0.1 mm and less than or equal to approximately 0.5 mm, for example.", (This puts the total surface area in a range of 0.008 mm^2 - 0.196 mm^2, the upper bound of which is greater than the minimum surface area of 0.1 mm^2 given by the present application)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked power converter assembly as described by the combination of Moss, Martinez, and Tsai with the surface area of the metal strips of Nishizawa so that "the conductive posts are respectively bonded to the semiconductor elements", (Nishizawa, [0043]).
Claim(s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moss (US 20150070850 A1), in view of Martinez (US 9867285 B2) and Glasscock (US 20200266133 A1).
Regarding dependent claim 30, Moss, as previously modified by Martinez, teaches the stacked power converter assembly according to claim 21. However, as previously combined, they do not teach wherein the one or more current-carrying metal strips are zero-ohm SMD resistors and/or SMD capacitors.
However, in the same field of endeavor, Glasscock teaches wherein the one or more current-carrying metal strips are zero-ohm SMD resistors and/or SMD capacitors (Fig. 1C, 121a, 121b; [0016], "...also known as a Surface Mount Device (SMD), capacitors, with a capacitor 121 shown that includes metal end caps 121a and 121b which provide electrical contact to each of its electrodes, where metal end cap 121b is available for bonding its bottom side to land pads of a PCB, with the other lead terminal is shown as a metal bar 126.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked power converter assembly as described by the combination of Moss and Martinez with the SMD capacitors of Glasscock "for generally realizing at least one circuit function", (Glasscock, [0017]).
Claim(s) 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moss (US 20150070850 A1), in view of Martinez (US 9867285 B2) and Zhang (US 20200212020 A1).
Regarding dependent claim 31, Moss, as previously modified by Martinez, teaches the stacked power converter assembly according to claim 21. However, as previously combined, they do not teach wherein the one or more current-carrying metal strips comprises at least one resistor at one end of the interposer, and at least one capacitor at an opposite end of the interposer.
However, in the same field of endeavor, Zhang teaches wherein the one or more current-carrying metal strips comprises at least one resistor at one end of the interposer, and at least one capacitor at an opposite end of the interposer (Fig. 1, 190, 114-2; [0035], "In other embodiments, the die 114-2 may include active or passive circuitry (e.g., transistors, diodes, resistors, inductors, and capacitors, among others). ", [0029], "Although FIG. 1 shows one capacitor 190…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked power converter assembly as described by the combination of Moss and Martinez with the capacitors and resistors of Zhang so that "signals may be transmitted between the package substrate and one or more dies", (Zhang, [0035]).
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moss (US 20150070850 A1), in view of Martinez (US 9867285 B2), Zhang (US 20200212020 A1), Glasscock (US 20200266133 A1), and Hoang (US 10602612 B1).
Regarding dependent claim 32, Moss, as previously modified by Martinez and Zhang, teaches the stacked power converter assembly according to claim 31. However, as previously combined, they do not teach wherein the at least one resistor is a zero ohm resistor, and wherein the at least one capacitor is an SMD capacitor.
However, in the same field of endeavor, Hoang teaches wherein the at least one resistor is a zero ohm resistor (Fig. 3, 310; (Col. 7, Lines 56-58), "In some embodiments, one or more vertical interconnects 310 may be “dummy” devices, such as zero ohm resistors."), and Glasscock teaches wherein the at least one capacitor is an SMD capacitor (Fig. 1C, 121a, 121b; [0016], "...also known as a Surface Mount Device (SMD), capacitors, with a capacitor 121 shown that includes metal end caps 121a and 121b which provide electrical contact to each of its electrodes, where metal end cap 121b is available for bonding its bottom side to land pads of a PCB, with the other lead terminal is shown as a metal bar 126.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked power converter assembly as described by the combination of Moss, Martinez, and Zhang with the zero ohm resistors of Hoang so as to "be dummy devices", (Hoang, Col. 7, Line 57), and with the SMD capacitor of Glasscock "for generally realizing at least one circuit function", (Glasscock, [0017]).
Claim(s) 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moss (US 20150070850 A1), in view of Martinez (US 9867285 B2), Tsai (US 20200411444 A1), and Lu (US 20160254217 A1).
Regarding dependent claim 33, Moss, as previously modified by Martinez, teaches the stacked power converter assembly according to claim 21. However, as previously combined, they do not teach wherein the one or more current-carrying metal strips are metal jumpers and/or wherein the one or more current-carrying metal strips are metal clips.
However, in the same field of endeavor, Tsai teaches wherein the one or more current-carrying metal strips are metal jumpers (Fig. 2D, 230, 236; [0061], "The conductive features 230 are substantially aligned with the conductive elements 110, as shown in FIG. 2B.", [0066], "...the support element 226 is a metal pillar..." (Using Broadest Reasonable Interpretation, these pillars are metal jumpers)), and Lu teaches and/or wherein the one or more current-carrying metal strips are metal clips (Fig. 5, 370; [0065], "The power device die 110 in the package module 30 of the power conversion circuit may also be electrically coupled to the substrate 100 by means of a metal clip 370, such as a cooper clip.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked power converter assembly as described by the combination of Moss and Martinez with the metal jumpers of Tsai for "providing electrical connection", (Tsai, [0023]), and with the metal clips of Lu "for electrically coupling the power device dies", (Lu, [0015]).
Claim(s) 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moss (US 20150070850 A1), in view of Martinez (US 9867285 B2), Tsai (US 20200411444 A1), and Lambert (US 20200006305 A1).
Regarding dependent claim 35, Moss, as previously modified by Martinez and Tsai, teaches the stacked power converter assembly according to claim 34. However, as previously combined, they do not teach wherein the molding material further encapsulates the one or more electrical passive components.
However, in the same field of endeavor, Lambert teaches wherein the molding material further encapsulates the one or more electrical passive components (Fig. 2, 221, 211; [0054], "In another example, the inductor may be air core inductor (ACI) on the substrate 250. In some other embodiments (and although not illustrated in FIG. 2), a passive component (e.g., an inductor) is included in one of the dies 211, 213.", [0055], "The dies 211, 213 may be encapsulated with an encapsulant or molding compound 221.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked power converter assembly as described by the combination of Moss, Martinez, and Tsai with the molding material of Lambert so as to dissipate heat, (Lambert, [0055]).
Claim(s) 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moss (US 20150070850 A1), in view of Martinez (US 9867285 B2) and Lambert (US 20200006305 A1).
Regarding dependent claim 37, Moss, as previously modified by Martinez, teaches the stacked power converter assembly according to claim 21. However, as previously combined, they do not teach wherein the stacked power converter assembly is a DC-DC power converter assembly, wherein the DC-DC power converter has multiple input voltage levels and multiple output voltage levels, and wherein the one or more integrated circuits is configured to manage a number of power conversion rates between the input voltage levels and output voltage levels.
However, in the same field of endeavor, Lambert teaches wherein the stacked power converter assembly is a DC-DC power converter assembly, wherein the DC-DC power converter has multiple input voltage levels and multiple output voltage levels ([0035], "For example, the power converter 104 may convert a Direct Current (DC) or Alternating Current (AC) voltage level to another DC or AC voltage level."), and wherein the one or more integrated circuits is configured to manage a number of power conversion rates between the input voltage levels and output voltage levels ([0036], "For example, the circuitries 120 may allocate power budgets to various components of the computing system, monitor power consumption of the various components of the computing system, dynamically update the power budgets, allocate operating voltage and/or frequency to the various components of the computing system, communicate with a battery circuitry to estimate remaining battery power, communicate with the power converter 104, and/or the like.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked power converter assembly as described by the combination of Moss and Martinez with the DC-DC power conversion function of Lambert "for managing power of a computing device", (Lambert, [0014]).
Claim(s) 38 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moss (US 20150070850 A1), in view of Martinez (US 9867285 B2) and Lu (US 20200286980 A1, hereinafter Lu2).
Regarding dependent claim 38, Moss, as previously modified by Martinez, teaches the stacked power converter assembly according to claim 21. However, as previously combined, they do not teach further comprising one or more secondary passive electrical components arranged on and connected to the interposer.
However, in the same field of endeavor, Lu2 teaches further comprising one or more secondary passive electrical components arranged on and connected to the interposer (Fig. 2A, 209; [0052], "...the electronic device 209 can be a passive device such as a capacitor, resistor or an inductor. The magnetic device 201 comprises an inductor, which can be a choke.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the stacked power converter assembly as described by the combination of Moss and Martinez with the secondary components on the interposer of Lu2 "for reducing the surface area occupied by the electronic structures", (Lu2, [0004]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20200350255 A1,.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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