Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 20190123093 A1), in view of Wang (US 20160086984 A1).
Regarding independent claim 1, Watanabe teaches a solid-state imaging device comprising: a first pixel including a first photoelectric conversion element that is disposed on a side of a first surface of a base and converts light into electric charge (Fig. 3, PD; [0007], "The photodiode is a photoelectric conversion element which generates and accumulates signal charges in accordance with the light receiving amount…", [0011], "The photodiode PD includes a p-type high concentration impurity region (p+region) 206 formed on the surface side of the semiconductor substrate 203..."), the side of the first surface being a light incident side ([0015], "In the solid-state imaging device having the above configuration, light incident from the back side is photoelectrically converted by the photodiode PD…"); a second pixel being adjacent to the first pixel, and including a second photoelectric conversion element that is disposed on the side of the first surface of the base and converts light into electric charge (Fig. 3, (There is another pixel adjacent to the first, made of the same components), [0028], "The solid-state imaging device having plural pixels is configured by arranging plural pixels in a necessary pattern."); a first transistor disposed at a position corresponding to the first pixel on a side of a second surface of the base (Fig. 3, Tr; [0024], "...in this example, a transfer transistor Tr1, a reset transistor Tr2 and an amplification transistor Tr3 are formed on the front side of a semiconductor substrate 1112."), the first transistor including a pair of main electrodes (Fig. 6, 12a, 12b; [0195], "The charge readout transistor Tr includes two vertical gate electrodes 12a, 12b…"), the side of the second surface being a side opposite to the first surface (Fig. 3, (This is self explanatory); [0023], "...in this example, a transfer transistor Tr1, a reset transistor Tr2 and an amplification transistor Tr3 are formed on the front side of a semiconductor substrate 1112."); a second transistor disposed at a position corresponding to the second pixel on the side of the second surface of the base, the second transistor including a pair of main electrodes (Fig. 3, (There is another pixel adjacent to the first, made of the same componenets), [0028], "The solid-state imaging device having plural pixels is configured by arranging plural pixels in a necessary pattern."); a pixel separation region disposed between the first photoelectric conversion element and the first transistor and between the second photoelectric conversion element and the second transistor (Fig. 47, 10; [0197], "the photodiode region 60 is demarcated from adjacent pixels by a pixel isolation region 10…"), and the pixel separation region electrically and optically separating the first photoelectric conversion element and the first transistor from each other and electrically and optically separating the second photoelectric conversion element and the second transistor from each other (Fig. 47, 10; [0197], "the photodiode region 60 is demarcated from adjacent pixels by a pixel isolation region 10…").
However, Watanabe does not teach and a shared coupling section having one end electrically coupled directly to one of the main electrodes of the first transistor, and another end electrically coupled, across the pixel separation region, directly to one of the main electrodes of the second transistor.
However, in the same field of endeavor, Wang teaches and a shared coupling section having one end electrically coupled directly to one of the main electrodes of the first transistor, and another end electrically coupled, across the pixel separation region, directly to one of the main electrodes of the second transistor (Fig. 1B, 126, 122b; [0021], "A floating diffusion node (FDN) 126 of the APS 102 is arranged over the peripheral isolation region 106 in electrical communication with the channel regions 116 of the transfer transistors 114.").
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the solid-state imaging device of Watanabe with the coupling section of Wang so as to "selectively transfer charge from the photodetectors", (Wang, [0029]).
Regarding dependent claim 2, Watanabe, as previously modified by Wang, teaches the solid-state imaging device according to claim 1. However, as previously combined, they do not teach wherein the one end of the shared coupling section is directly coupled to a side surface of the one of the main electrodes of the first transistor, and the other end of the shared coupling section is directly coupled to a side surface of the one of the main electrodes of the second transistor.
However, Wang further teaches wherein the one end of the shared coupling section is directly coupled to a side surface of the one of the main electrodes of the first transistor, and the other end of the shared coupling section is directly coupled to a side surface of the one of the main electrodes of the second transistor (Fig. 1B, 126, 122a; [0021], "A floating diffusion node (FDN) 126 of the APS 102 is arranged over the peripheral isolation region 106 in electrical communication with the channel regions 116 of the transfer transistors 114.", (Given that the connection region also functions as the source and drain, it can be said to be directly coupled to the side of these structures)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the solid-state imaging device as described by the combination of Watanabe and Wang with the position of the coupling section of Wang so as to "selectively transfer charge from the photodetectors", (Wang, [0029]).
Regarding dependent claim 3, Watanabe, as previously modified by Wang, teaches the solid-state imaging device according to claim 2. However, as previously combined, they do not teach wherein the shared coupling section is embedded in a shared trench formed from the second surface of the pixel separation region toward the first surface of the pixel separation region.
However, Wang further teaches wherein the shared coupling section is embedded in a shared trench formed from the second surface of the pixel separation region toward the first surface of the pixel separation region (Fig. 1B, 126, 106, (The connection region cuts into one side of the separation region 106)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the solid-state imaging device as described by the combination of Watanabe and Wang with the trench of Wang so as to be "in electrical communication with the channel region", (Wang, [0038]).
Regarding dependent claim 12, Watanabe, as previously modified by Wang, teaches the solid-state imaging device according to claim 1, and further teaches wherein the first transistor and the second transistor respectively comprise an amplification transistor and a selection transistor ([0608], "The plural pixel transistors include, for example, three transistors, for example, a transfer transistor, a reset transistor and an amplification transistor. It may include four transistors by adding a selection transistor.").
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 20190123093 A1), in view of Wang (US 20160086984 A1) and Nagahama (US 20210343776 A1).
Regarding dependent claim 4, Watanabe, as previously modified by Wang, teaches the solid-state imaging device according to claim 1. However, as previously combined, they do not teach wherein the one end of the shared coupling section is directly coupled to a surface of the one of the main electrodes of the first transistor, and the other end of the shared coupling section is directly coupled to a surface of the one of the main electrodes of the second transistor.
However, in the same field of endeavor, Nagahama teaches wherein the one end of the shared coupling section is directly coupled to a surface of the one of the main electrodes of the first transistor, and the other end of the shared coupling section is directly coupled to a surface of the one of the main electrodes of the second transistor (Fig. 20, TR, 301a,b, 222; [0134], "As described above, in this example, the source region 222 of the transfer transistor TR is an N-type semiconductor region, so the wiring 301a connected to the source region 222 is formed as P-type polysilicon. On the other hand, the electrode 230 is P-type polysilicon, so the wiring 301b connected to the electrode 230 is formed as N-type polysilicon.").
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the solid-state imaging device as described by the combination of Watanabe and Wang with the direct coupling of Nagahama so as to "aggregate the plurality of electrodes", (Nagahama, [0133]).
Regarding dependent claim 5, Watanabe, as previously modified by Wang and Nagahama, teaches the solid-state imaging device according to claim 4. However, as previously combined, they do not teach wherein the shared coupling section is formed to intersect the pixel separation region on the second surface of the base.
However, Wang further teaches wherein the shared coupling section is formed to intersect the pixel separation region on the second surface of the base (Fig. 1B, 126, 106, (The connection region cuts into one side of the separation region 106)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the solid-state imaging device as described by the combination of Watanabe, Wang, and Nagahama with the intersection of Wang so as to "selectively transfer charge from the photodetectors", (Wang, [0029]).
Regarding dependent claim 6, Watanabe, as previously modified by Wang and Nagahama, teaches the solid-state imaging device according to claim 1. However, as previously combined, they do not teach wherein the shared coupling section includes a gate electrode material.
However, Nagahama further teaches wherein the shared coupling section includes a gate electrode material (Fig. 20, TR, 301a,b, 222; [0134], "As described above, in this example, the source region 222 of the transfer transistor TR is an N-type semiconductor region, so the wiring 301a connected to the source region 222 is formed as P-type polysilicon.", (Since the present application gives the example of polysilicon for "gate electrode material", this art can be said to teach said material)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the solid-state imaging device as described by the combination of Watanabe, Wang, and Nagahama with the gate electrode material of Nagahama for connecting to "an N-type semiconductor region", (Nagahama, [0134]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 20190123093 A1), in view of Wang (US 20160086984 A1) and Sano (US 20190342510 A1).
Regarding dependent claim 7, Watanabe, as previously modified by Wang, teaches the solid-state imaging device according to claim 1. However, as previously combined, they do not teach wherein the pixel separation region has a first trench having a depth direction in a thickness direction of the base, and includes a first embedded member embedded in the first trench.
However, in the same field of endeavor, Sano teaches wherein the pixel separation region has a first trench having a depth direction in a thickness direction of the base (Fig. 22, 441-1,2; [0353], "For example, when the separation region 441 is formed, a longitudinal groove (trench) is formed in a downward direction (in a direction vertical to the surface of the substrate 61)…"), and includes a first embedded member embedded in the first trench ([0353], "...and the light shielding film is formed by being embedded in the groove portion, and thus, the separation region 441 is formed.").
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the solid-state imaging device as described by the combination of Watanabe and Wang with the trench and embedded member of Sano so as to "improve the separation characteristics of the light between the pixels, and to suppress the occurrence of the color mixture", (Sano, [0354]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 20190123093 A1), in view of Wang (US 20160086984 A1), Sano (US 20190342510 A1), and Nam (US 20180130806 A1).
Regarding dependent claim 8, Watanabe, as previously modified by Wang and Sano, teaches the solid-state imaging device according to claim 7. However, as previously combined, they do not teach wherein each of the first transistor and the second transistor is surrounded by an element separation region having a second trench and including a second embedded member and is electrically separated from another region, the second trench being formed from the second surface of the base toward the side of the first surface of the base and having a depth shallower than that of the first trench, the second embedded member being embedded in the second trench.
However, in the same field of endeavor, Nam teaches wherein each of the first transistor and the second transistor is surrounded by an element separation region having a second trench and including a second embedded member and is electrically separated from another region, the second trench being formed from the second surface of the base toward the side of the first surface of the base and having a depth shallower than that of the first trench, the second embedded member being embedded in the second trench (Fig. 2A, 16s, 15; [0032], "...the second portion of the gate trench 15 embedded in the element isolation region 16s…").
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the solid-state imaging device as described by the combination of Watanabe, Wang, and Sano with the element separation region of Nam for "defining the active region", (Nam, [0005]).
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 20190123093 A1), in view of Wang (US 20160086984 A1), Sano (US 20190342510 A1), Nam (US 20180130806 A1), and Hwang (US 20180102392 A1).
Regarding dependent claim 9, Watanabe, as previously modified by Wang, Sano, and Nam, teaches the solid-state imaging device according to claim 8. However, as previously combined, they do not teach wherein a direction of a gate length of each of the first transistor and the second transistor is oblique to an extending direction of the pixel separation region.
However, in the same field of endeavor, Hwang teaches wherein a direction of a gate length of each of the first transistor and the second transistor is oblique to an extending direction of the pixel separation region (Fig. 12, TX1-4, (They are all in diagonal directions, while the pixels are laid out in cardinal directions)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the solid-state imaging device as described by the combination of Watanabe, Wang, Sano, and Nam with the oblique directions of Hwang so that "the recess pattern is formed to be disposed at the center of the photoelectric conversion element while providing a space for the pixel transistors", (Hwang, [0121]).
Regarding dependent claim 10, Watanabe, as previously modified by Wang, Sano, and Nam, teaches the solid-state imaging device according to claim 8. However, as previously combined, they do not teach wherein a direction of a gate length of each of the first transistor and the second transistor is formed at an angle of 45 degrees with respect to an extending direction of the pixel separation region.
However, in the same field of endeavor, Hwang teaches wherein a direction of a gate length of each of the first transistor and the second transistor is formed at an angle of 45 degrees with respect to an extending direction of the pixel separation region ([0055], "Herein, the first direction D1 and the second direction D2 may refer to a diagonal direction have a predetermined gradient based on a row direction RD or a column direction CD. The predetermined gradient may be approximately ±45°.").
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the solid-state imaging device as described by the combination of Watanabe, Wang, Sano, and Nam with the 45 degree angle of Hwang so that "the recess pattern is formed to be disposed at the center of the photoelectric conversion element while providing a space for the pixel transistors", (Hwang, [0121]).
Regarding dependent claim 11, Watanabe, as previously modified by Wang, Sano, Nam, and Hwang, teaches the solid-state imaging device according to claim 10, and further teaches wherein at least one of a floating diffusion region, a control electrode of a transfer transistor, or a base coupling section is disposed in a direction of a gate width of each of the first transistor and the second transistor (Fig. 3, 1117; [0025], "...an n-type source/drain region 1117 to be a floating diffusion (FD) 40 is formed…"), the floating diffusion region transferring the converted electric charge ([0616], "Signal charges (electrons in the example) which have been photoelectrically converted and accumulated in the photodiode PD are transferred to the floating diffusion (FD) by application of a transfer pulse to a transfer gate."), the control electrode controlling the transferring of the electric charge, the base coupling section supplying the base with a voltage.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 20190123093 A1), in view of Wang (US 20160086984 A1) and Kobayashi (US 20190253659 A1).
Regarding dependent claim 13, Watanabe, as previously modified by Wang, teaches the solid-state imaging device according to claim 1. However, as previously combined, they do not teach wherein the first transistor and the second transistor construct a pixel circuit that processes the converted electric charge.
However, in the same field of endeavor, Kobayashi teaches wherein the first transistor and the second transistor construct a pixel circuit that processes the converted electric charge ([0194], "As described above, the pixel circuit of the pixel 100 includes two transistors having different sizes.").
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the solid-state imaging device as described by the combination of Watanabe and Wang with the pixel circuit of Kobayashi so that "the electric characteristics can be improved", (Kobayashi, [0194]).
Claim(s) 14, 16, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 20190123093 A1), in view of Wang (US 20160086984 A1) and Hwang (US 20180102392 A1).
Regarding dependent claim 14, Watanabe, as previously modified by Wang, teaches the solid-state imaging device according to claim 1. However, as previously combined, they do not teach further comprising: a third pixel including a third photoelectric conversion element that is disposed on the side of the first surface of the base and converts light into electric charge; a fourth pixel being adjacent to the third pixel, and including a fourth photoelectric conversion element that is disposed on the side of the first surface of the base and converts light into electric charge; a third transistor disposed at a position corresponding to the third pixel on the side of the second surface of the base, the third transistor including a pair of main electrodes; a fourth transistor disposed at a position corresponding to the fourth pixel on the side of the second surface of the base, the fourth transistor including a pair of main electrodes; and a shared coupling section having one end electrically coupled directly to one of the main electrodes of the third transistor, and another end electrically coupled, across the pixel separation region, directly to one of the main electrodes of the fourth transistor.
However, in the same field of endeavor, Hwang teaches a third pixel including a third photoelectric conversion element that is disposed on the side of the first surface of the base and converts light into electric charge; a fourth pixel being adjacent to the third pixel, and including a fourth photoelectric conversion element that is disposed on the side of the first surface of the base and converts light into electric charge (Fig. 12, 110-3,110-4; [0016], "...the plurality of the sub-arrays includes a first unit pixel, a second unit pixel, a third unit pixel, and a fourth unit pixel..."); a third transistor disposed at a position corresponding to the third pixel on the side of the second surface of the base (Fig. 12, 220-3, Fig. 5B, 220, PD; [0061], "The photoelectric conversion element PD may be formed to contact the back side BS of the substrate 200…", (Meaning that the transistor, which is on the opposite side, is on the front side)), the third transistor including a pair of main electrodes (Fig. 5B, 220, 230; [0070], "The first gate 220 may include a first gate insulating layer 220B and a first gate electrode 220A…", [0074], "The third gate 240 may include the third gate insulating layer 240B and the third gate electrode 240A…"); a fourth transistor disposed at a position corresponding to the fourth pixel on the side of the second surface of the base (Fig. 12, 220-4, Fig. 5B, 220, PD; [0061], "The photoelectric conversion element PD may be formed to contact the back side BS of the substrate 200…", (Meaning that the transistor, which is on the opposite side, is on the front side)), the fourth transistor including a pair of main electrodes (Fig. 5B, 220, 230; [0070], "The first gate 220 may include a first gate insulating layer 220B and a first gate electrode 220A…", [0074], "The third gate 240 may include the third gate insulating layer 240B and the third gate electrode 240A…"); and Wang further teaches and a shared coupling section having one end electrically coupled directly to one of the main electrodes of the third transistor, and another end electrically coupled, across the pixel separation region, directly to one of the main electrodes of the fourth transistor (Fig. 1B, 126, 122a,b; [0021], "A floating diffusion node (FDN) 126 of the APS 102 is arranged over the peripheral isolation region 106 in electrical communication with the channel regions 116 of the transfer transistors 114.").
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the solid-state imaging device as described by the combination of Watanabe and Wang with the additional pixels of Hwang so as to create "an image sensor capable of providing a high-pixel image", (Hwang, [0041]), and the coupling section of Wang so as to "selectively transfer charge from the photodetectors", (Wang, [0029]).
Regarding dependent claim 16, Watanabe, as previously modified by Wang and Hwang, teaches the solid-state imaging device according to claim 14. However, as previously combined, they do not teach wherein the first pixel and the second pixel are arranged to be adjacent to each other in a first direction, and the third pixel and the fourth pixel are arranged to be adjacent to the first pixel and the second pixel in a second direction intersecting the first direction and to be adjacent to each other in the first direction.
However, Hwang further teaches wherein the first pixel and the second pixel are arranged to be adjacent to each other in a first direction, and the third pixel and the fourth pixel are arranged to be adjacent to the first pixel and the second pixel in a second direction intersecting the first direction and to be adjacent to each other in the first direction (Fig. 12, 110-1-4, (The pixels 110-1-4 are arranged in grid fashion, and so satisfy this limitation); [0043], "The pixel array 100 may include a plurality of unit pixels 110 arranged in a matrix.").
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the solid-state imaging device as described by the combination of Watanabe, Wang, and Hwang with the pixel layout of Hwang so as to create "an image sensor capable of providing a high-pixel image", (Hwang, [0041]).
Regarding dependent claim 17, Watanabe, as previously modified by Wang and Hwang, teaches the solid-state imaging device according to claim 16. However, as previously combined, they do not teach wherein a planar shape of the first transistor and the second transistor is a shape formed in line symmetry with respect to the pixel separation region disposed between both the first transistor and the second transistor, and a planar shape of the third transistor and the fourth transistor is a shape formed in line symmetry with respect to the pixel separation region disposed between both the third transistor and the fourth transistor.
However, Hwang further teaches wherein a planar shape of the first transistor and the second transistor is a shape formed in line symmetry with respect to the pixel separation region disposed between both the first transistor and the second transistor (Fig. 12, TX1, TX2, (They have (reflectional) line symmetry); [0113], "...the unit pixels 110-1 to 110-4 may have a planar shape that is symmetrical in a row direction RD and a column direction CD."), and a planar shape of the third transistor and the fourth transistor is a shape formed in line symmetry with respect to the pixel separation region disposed between both the third transistor and the fourth transistor (Fig. 12, TX3, TX4, (They have (reflectional) line symmetry); [0113], "...the unit pixels 110-1 to 110-4 may have a planar shape that is symmetrical in a row direction RD and a column direction CD.").
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the solid-state imaging device as described by the combination of Watanabe, Wang, and Hwang with the symmetry of Hwang "for the purpose of stabilization in the production yield", (Hwang, [0115]).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 20190123093 A1), in view of Wang (US 20160086984 A1), Hwang (US 20180102392 A1), and Fukusaku (US 20210391366 A1).
Regarding dependent claim 15, Watanabe, as previously modified by Wang and Hwang, teaches the solid-state imaging device according to claim 14. However, as previously combined, they do not teach wherein the third transistor and the fourth transistor respectively comprise a floating diffusion conversion gain switching transistor and a reset transistor.
However, in the same field of endeavor, Fukusaku teaches wherein the third transistor and the fourth transistor respectively comprise a floating diffusion conversion gain switching transistor and a reset transistor (Fig. 71, FDG, RST; [0353], "The pixel circuit 210 includes, for example, four transistors, which specifically are an amplifying transistor AMP, a selecting transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FD.").
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the solid-state imaging device as described by the combination of Watanabe, Wang, and Hwang with the transistor types of Fukusaku "for changing the gain of the charge-to voltage conversion at the floating diffusion FD", (Fukusaku, [0358]).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 20190123093 A1), in view of Wang (US 20160086984 A1), Shin (US 20210383555 A1), and Honda (US 20180302597 A1).
Regarding dependent claim 18, Watanabe, as previously modified by Wang, teaches the solid-state imaging device according to claim 1. However, as previously combined, they do not teach further comprising: a color filter disposed across at least the first pixel and the second pixel in a first direction and having the same color; and an optical lens disposed on a side of the color filter opposite to the first pixel and the second pixel, the optical lens having a length in a second direction shorter than a length in the first direction, the second direction intersecting the first direction, wherein another one of the first pixel and another one of the second pixel adjacent to the first pixel and the second pixel in the second direction are arranged to be shifted by one pixel in the first direction with respect to the first pixel and the second pixel.
However, in the same field of endeavor, Shin teaches a color filter disposed across at least the first pixel and the second pixel in a first direction and having the same color (Fig, 3, PG1, CF1; [0050], "Color filters CF1 to CF4 for passing a light of a specific type (e.g., specific wavelength band) may be respectively formed on the pixel groups PG1 to PG4."); and an optical lens disposed on a side of the color filter opposite to the first pixel and the second pixel, the optical lens having a length in a second direction shorter than a length in the first direction, the second direction intersecting the first direction (Fig. 4, ML; [0050], "A micro lens ML may be formed on a color filter formed on each pixel.", (In addition, the diagram shows that the lens is oblong, therefore it has a length in a second direction shorter than a length in the first)), and Honda teaches wherein another one of the first pixel and another one of the second pixel adjacent to the first pixel and the second pixel in the second direction are arranged to be shifted by one pixel in the first direction with respect to the first pixel and the second pixel (Fig. 3, R, B, (Each group of 4 square elements is either and R or a B square and they are offset from each other by one pixel); [0057], "...the color pixels are arranged at positions shifted from the polarizing pixels in the row direction and in the column direction between the adjacent polarizing pixels in the row direction and the column direction in a grid form (a matrix form).").
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the solid-state imaging device as described by the combination of Watanabe and Wang with the color filter and optical lens of Shin so that the pixels can "share a floating diffusion region", (Shin, [0004]), and the shifted pixels of Honda so as "to improve the detection accuracy", (Honda, [0005]).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 20190123093 A1), in view of Wang (US 20160086984 A1) and Hayashi (US 20170155857 A1).
Regarding dependent claim 19, Watanabe, as previously modified by Wang, teaches the solid-state imaging device according to claim 1. However, as previously combined, they do not teach further comprising a dummy pixel that adjusts capacitance of a floating diffusion region.
However, in the same field of endeavor, Hayashi teaches further comprising a dummy pixel that adjusts capacitance of a floating diffusion region ([0093], "A pixel array 1000 has a NULL pixel region 1000a having NULL pixels (dummy pixels)…", [0099], " In other words, the output timing of the second output permission signal is delayed to be in synchronism with a start of shutter scanning after the readout scanning on the NULL pixel region 1000a is started and the readout scanning on the OB pixel region 1000b is started.").
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the solid-state imaging device as described by the combination of Watanabe and Wang with the dummy pixel of Hayashi "so that highly accurate imaging can be performed", (Hayashi, [0093]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210273006 A1,.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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